JPS59172756A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS59172756A
JPS59172756A JP4743383A JP4743383A JPS59172756A JP S59172756 A JPS59172756 A JP S59172756A JP 4743383 A JP4743383 A JP 4743383A JP 4743383 A JP4743383 A JP 4743383A JP S59172756 A JPS59172756 A JP S59172756A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
covered
semiconductor element
thin metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4743383A
Other languages
Japanese (ja)
Inventor
Masanori Matsuo
松尾　政則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4743383A priority Critical patent/JPS59172756A/en
Publication of JPS59172756A publication Critical patent/JPS59172756A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain a semiconductor element having stable reliability by preventing the contact failure of said element by a method wherein the outer periphery of the surface of a connecting electrode prt is covered with an insulation film. CONSTITUTION:The outer peripheries of the connecting electrode parts 3 and 4 of a semiconductor element are covered with the insulation films 5. Thereby, the adhesion of a metallic fine wire and the electrode end part is eliminated, thus enabling to remove electrode stripping (generated from the electrode end parts).

Description

【発明の詳細な説明】 本発明はトランジスタ、集積回路などの半導体素子の結
線用電極部を有する半導体素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a connection electrode portion for semiconductor devices such as transistors and integrated circuits.

一般に半導体回路素子は金属細線（ボンディング線）で
結線され電気的接続を行なうが、この雅の半導体素子の
結線用電極部は例えば８ｇ１図及び第２図に示すような
ものであった。Semiconductor circuit elements are generally wired with thin metal wires (bonding wires) for electrical connection, and the electrode portions for connection of this Miyabi semiconductor element were as shown in Figures 8g1 and 2, for example.

即ちＰＮ接合１の保護及び表面絶縁分離のための絶縁被
膜２が形成され、そしてエミッタ電極３及びベース電極
４が形成される。この場合、金属細線で接続される電極
部と絶縁被膜は平滑面で対抗しているため、両者の接着
強度は接着面積に依存している。特に高周波帯の素子は
寄生容量の減少を図るため、金属細線で接続される電極
部は小さい面積となっているため、次の様な欠点を有し
ている。That is, an insulating film 2 for protecting the PN junction 1 and for surface insulation isolation is formed, and then an emitter electrode 3 and a base electrode 4 are formed. In this case, since the electrode portion connected by the thin metal wire and the insulating coating face each other on a smooth surface, the adhesive strength between the two depends on the adhesive area. Particularly in high frequency band devices, in order to reduce parasitic capacitance, the electrode portions connected by thin metal wires have a small area, so they have the following drawbacks.

１　金属細線で結線を行なう場合、高温状態で圧着する
が、そのストレスによυ電極が絶縁被膜から剥れる。1. When connecting with thin metal wires, they are crimped at high temperatures, but the stress causes the υ electrodes to peel off from the insulation coating.

２　金属細線で結線し、樹脂封止を行なった場合樹脂の
膨張歪によシミ極が絶縁被膜から剥れる。2. When connecting with thin metal wire and sealing with resin, the stain electrode will peel off from the insulation coating due to expansion strain of the resin.

剥れのモードとしては電極端からのめくれ現象が多く、
半導体素子の接続不良を誘発し、信頼度の優れた半導体
素子を供給することができない。The most common mode of peeling is peeling off from the electrode end.
This causes poor connection of semiconductor elements, making it impossible to supply semiconductor elements with excellent reliability.

本発明の目的は上記の欠点を解決するために提案された
もので安定した信頼度を有する半導体素子を提供するこ
とにある。この目的の゛ために、本発明の半導体装置は
、結線用型！部表面の外周部を絶縁膜で被うことを特徴
とする特 以下、本発明の実施例を図面によって詳細に説明する。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has been proposed to solve the above-mentioned drawbacks and has stable reliability. For this purpose, the semiconductor device of the present invention is of a wiring type! Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第３図及び第４図は本発明の一実施例を示すトランジス
タの平面図及び断面図である。７結線用電極部の外周部
をＰ縁膜で被うことによシ、金属細線と電極端部の接着
をなくシ、電極側れ（Ｎ極端部よシ発生する）を々くす
ことができる。3 and 4 are a plan view and a sectional view of a transistor showing an embodiment of the present invention. 7. By covering the outer periphery of the connection electrode part with a P membrane, it is possible to eliminate adhesion between the thin metal wire and the electrode end, and to reduce electrode side deviation (which occurs at the N end). .

熱論との方式はトランジスタに限らず、金属細線で接続
を行々う集積回路ガどの半導体素子全般にも適用できる
。The method with thermal theory can be applied not only to transistors but also to all semiconductor devices such as integrated circuits that are connected using thin metal wires.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のトランジスタの平面図、第２図は従来の
トランジスタの断面図、第３図は本発明の一実施例を示
す平面図、第４図は本発明の一実施例を示す断面図であ
る。Fig. 1 is a plan view of a conventional transistor, Fig. 2 is a cross-sectional view of a conventional transistor, Fig. 3 is a plan view showing an embodiment of the present invention, and Fig. 4 is a cross-section showing an embodiment of the present invention. It is a diagram.

Claims (1)

【特許請求の範囲】[Claims] 半導体素子の少なくとも結線用電極表面の外周部を絶縁
膜によシ被っていることを特徴とする半導体装置。A semiconductor device characterized in that at least the outer periphery of a surface of a wiring electrode of a semiconductor element is covered with an insulating film.
JP4743383A 1983-03-22 1983-03-22 Semiconductor device Pending JPS59172756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4743383A JPS59172756A (en) 1983-03-22 1983-03-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4743383A JPS59172756A (en) 1983-03-22 1983-03-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS59172756A true JPS59172756A (en) 1984-09-29

Family

ID=12775014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4743383A Pending JPS59172756A (en) 1983-03-22 1983-03-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59172756A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997023904A1 (en) * 1995-12-21 1997-07-03 Siemens Matsushita Components Gmbh & Co. Kg Process for producing contacts on electrical components suitable for a flip-chip assembly
JP4864696B2 (en) * 2003-04-23 2012-02-01 ボルボ エアロ コーポレイション Method and apparatus for reducing contamination of workpieces

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028271A (en) * 1973-07-13 1975-03-22
JPS5192172A (en) * 1975-02-10 1976-08-12 Denkyokuhyomen oo taishokuseihogomaku no keiseihoho

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5028271A (en) * 1973-07-13 1975-03-22
JPS5192172A (en) * 1975-02-10 1976-08-12 Denkyokuhyomen oo taishokuseihogomaku no keiseihoho

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997023904A1 (en) * 1995-12-21 1997-07-03 Siemens Matsushita Components Gmbh & Co. Kg Process for producing contacts on electrical components suitable for a flip-chip assembly
JP4864696B2 (en) * 2003-04-23 2012-02-01 ボルボ エアロ コーポレイション Method and apparatus for reducing contamination of workpieces

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