JP2001196505A - Resin sealed semiconductor package with its chip surface exposed - Google Patents
Resin sealed semiconductor package with its chip surface exposedInfo
- Publication number
- JP2001196505A JP2001196505A JP34916999A JP34916999A JP2001196505A JP 2001196505 A JP2001196505 A JP 2001196505A JP 34916999 A JP34916999 A JP 34916999A JP 34916999 A JP34916999 A JP 34916999A JP 2001196505 A JP2001196505 A JP 2001196505A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- resin
- exposed
- substrate
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップ表面
露出型の樹脂封止半導体パッケージに関し、特に半導体
チップと封止樹脂との接合界面との剥離の防止および当
該樹脂封止半導体パッケージの静電破壊を防止するよう
にした半導体チップ表面露出型の樹脂封止半導体パッケ
ージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor package having an exposed surface of a semiconductor chip, and more particularly, to the prevention of peeling of a bonding interface between a semiconductor chip and a sealing resin and the prevention of static electricity of the resin-sealed semiconductor package. The present invention relates to a semiconductor chip surface-exposed resin-sealed semiconductor package that prevents breakage.
【０００２】[0002]
【従来の技術】近年、個人認証・個人識別の手段の一つ
として当人の指紋を用いる場合がある。この場合には半
導体チップ表面露出型の樹脂封止半導体パッケージ（以
下、樹脂封止半導体パッケージと記す）の前記露出面に
指紋を接触させ、指紋識別を行うのが一般的である。2. Description of the Related Art In recent years, there is a case where a fingerprint of a person is used as one of means for personal authentication and personal identification. In this case, fingerprint identification is generally performed by bringing a fingerprint into contact with the exposed surface of a resin-sealed semiconductor package of a semiconductor chip surface-exposed type (hereinafter referred to as a resin-sealed semiconductor package).
【０００３】図３は、従来の樹脂封止半導体パッケージ
１００の外観斜視図、図４はIV−IV線に沿う断面図、図
５は樹脂封止の製造過程の断面図である。FIG. 3 is an external perspective view of a conventional resin-sealed semiconductor package 100, FIG. 4 is a cross-sectional view taken along the line IV-IV, and FIG. 5 is a cross-sectional view of a resin-sealing manufacturing process.
【０００４】ここで、図３〜図５を参照しつつ樹脂封止
半導体パッケージ１００の製造方法の一例を説明する。 ガラスエポキシ等からなる基板１０１上に半導体チッ
プ１０２を、導電性接着剤１０４を介して接着する（図
３，図４参照）。Here, an example of a method of manufacturing the resin-sealed semiconductor package 100 will be described with reference to FIGS. A semiconductor chip 102 is bonded on a substrate 101 made of glass epoxy or the like via a conductive adhesive 104 (see FIGS. 3 and 4).
【０００５】金属細線１０５で、半導体チップ１０２
の電極と基板１０１の電極とを結線する（図４参照）。 金型の上型１０６と下型１０７により基板１０１及び
半導体チップ１０２を挟み、封止用の樹脂を注入し、樹
脂の硬化後、上型１０６と下型１０７を開くとパッケー
ジ１００が完成する（図５参照）。１０３が硬化後の封
止樹脂である。[0005] The semiconductor chip 102 is formed by the thin metal wire 105.
Are connected to the electrodes of the substrate 101 (see FIG. 4). After the substrate 101 and the semiconductor chip 102 are sandwiched between the upper mold 106 and the lower mold 107, a sealing resin is injected, and after the resin is cured, the upper mold 106 and the lower mold 107 are opened to complete the package 100. (See FIG. 5). Reference numeral 103 denotes a cured sealing resin.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、この従
来構造の樹脂封止半導体パッケージ１００には次の問題
点がある。However, the resin-sealed semiconductor package 100 having the conventional structure has the following problems.
【０００７】第１の問題点は、半導体チップ１０２と
封止樹脂１０３の接合界面１１０（図４参照）における
剥離の発生である。この剥離が発生すると、例えば水分
の侵入により、金属細線１０５を接合させる半導体チッ
プ１０２のアルミ電極が腐食し、電気回路が正常に動作
しなくなるという問題がある。The first problem is the occurrence of peeling at the bonding interface 110 between the semiconductor chip 102 and the sealing resin 103 (see FIG. 4). When this peeling occurs, there is a problem that the aluminum electrode of the semiconductor chip 102 to which the thin metal wire 105 is bonded is corroded due to, for example, intrusion of moisture, and the electric circuit does not operate normally.
【０００８】この剥離発生の理由を説明する。図示省略
の電子装置等の基板（セット基板）に半導体チップ１０
２を実装する際、はんだ付けの温度は約２００〜２４０
℃である。このはんだ付けに伴う温度上昇により、半導
体チップ１０２と封止樹脂１０３との接合界面１１０
に、お互いの線膨張係数の違いによるせん断応力が発生
し、接合界面１１０に剥離が発生する場合がある。[0008] The reason for the occurrence of peeling will be described. A semiconductor chip 10 is mounted on a substrate (set substrate) of an electronic device or the like (not shown).
When mounting 2, the soldering temperature is about 200 to 240
° C. Due to the rise in temperature due to the soldering, a bonding interface 110 between the semiconductor chip 102 and the sealing resin 103 is formed.
In some cases, a shear stress is generated due to a difference between linear expansion coefficients, and peeling may occur at the bonding interface 110.
【０００９】ここに、周知事実として、シリコンの半導
体チップの線膨張係数は３．５×１０-6／℃、封止樹脂
の線膨張係数は約１５×１０-6／℃であり、異物間の接
合界面に働くせん断応力は、温度変化が大きくなると応
力も大きくなり、加えて接合面の距離が長くなると応力
も大きくなる、ということがある。Here, it is well known that the silicon semiconductor chip has a linear expansion coefficient of 3.5 × 10 −6 / ° C. and the sealing resin has a linear expansion coefficient of about 15 × 10 −6 / ° C. In some cases, the shear stress acting on the bonding interface increases as the temperature change increases, and in addition, the stress increases as the distance between the bonding surfaces increases.
【００１０】第２の問題点は、指紋識別の際に、その
人が高い電位の静電気を帯電している場合がある。この
場合には、半導体チップ１０２にその人の指が接触する
と、半導体チップ１０２が静電破壊を起す危険性があ
り、その結果、電気回路が正常に動作しなくなるという
問題点がある。[0010] The second problem is that, at the time of fingerprint identification, the person may be charged with high potential static electricity. In this case, when a person's finger comes into contact with the semiconductor chip 102, there is a risk that the semiconductor chip 102 may be damaged by static electricity. As a result, there is a problem that an electric circuit does not operate normally.
【００１１】そこで本発明の課題は、半田付け等によっ
ても半導体チップと封止樹脂との間の接合界面が剥離を
起さず、高電位に帯電した人の指が接触しても静電破壊
を起すことの無い半導体チップ表面露出型の樹脂封止半
導体パッケージを提供することである。An object of the present invention is to solve the problem that the bonding interface between the semiconductor chip and the sealing resin does not peel even by soldering or the like, and electrostatic breakdown occurs even when a high-potential person's finger comes into contact. An object of the present invention is to provide a resin-sealed semiconductor package of a semiconductor chip surface-exposed type which does not cause the problem.
【００１２】[0012]
【課題を解決するための手段】前記課題を解決するため
に本発明は、基板上に載置した板状の半導体チップの端
子と前記基板とを金属線により接続すると共に、前記金
属線および半導体チップを樹脂で封止しつつ、該半導体
チップの表面を露出させてなる半導体チップ表面露出型
の樹脂封止半導体パッケージにおいて、前記半導体チッ
プの側面と、前記半導体チップ上の金属線の接続箇所の
周辺のみを、樹脂で封止してなることを特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is to connect a terminal of a plate-shaped semiconductor chip mounted on a substrate to the substrate by a metal wire, and to connect the metal wire and the semiconductor to the substrate. In a semiconductor chip surface-exposed type resin-encapsulated semiconductor package in which the surface of the semiconductor chip is exposed while the chip is sealed with a resin, a side surface of the semiconductor chip and a connection portion of a metal wire on the semiconductor chip are connected. It is characterized in that only the periphery is sealed with a resin.
【００１３】このようにすれば、樹脂封止する箇所が金
属線の接続箇所の周辺のみなので、接合界面の長さが従
来品と比較して短くなる。従って、接合界面の剥離が発
生する確率を低く抑えることができる。In this case, since the portion to be sealed with the resin is only around the connecting portion of the metal wire, the length of the bonding interface is shorter than that of the conventional product. Therefore, the probability of occurrence of separation at the bonding interface can be reduced.
【００１４】また、前記半導体チップの露出面と前記封
止樹脂の上面とを同一面とするか、または前記封止樹脂
の上面を前記半導体チップの露出面より高くすることを
特徴とする。Further, the exposed surface of the semiconductor chip and the upper surface of the sealing resin are the same surface, or the upper surface of the sealing resin is higher than the exposed surface of the semiconductor chip.
【００１５】また、前記金属線の接続箇所以外の封止樹
脂部分に、前記基板に接続した金属電極を埋め込んだこ
とを特徴とする。このようにすれば、人の指等の帯電物
が樹脂封止半導体パッケージに触れた場合でも、金属電
極を介して基板のアースパターンに静電気が流れるの
で、樹脂封止半導体パッケージが静電破壊を起こすこと
がない。Further, a metal electrode connected to the substrate is buried in a sealing resin portion other than a connection portion of the metal wire. In this way, even when a charged object such as a human finger touches the resin-encapsulated semiconductor package, static electricity flows to the ground pattern of the substrate via the metal electrode, so that the resin-encapsulated semiconductor package causes electrostatic breakdown. Never wake up.
【００１６】また、前記半導体チップの露出面と前記金
属電極の上面とを同一面とするか、または前記金属電極
の上面を前記半導体チップの露出面より高くすることを
特徴とする。このようにすれば、半導体チップに人の指
等が触れる場合に、低い面となっている半導体チップの
露出面に触れるより先に金属電極の上面に接触するの
で、静電気が金属電極に流れ、静電破壊を起し難くな
る。The exposed surface of the semiconductor chip and the upper surface of the metal electrode may be flush with each other, or the upper surface of the metal electrode may be higher than the exposed surface of the semiconductor chip. In this way, when a person's finger or the like touches the semiconductor chip, the semiconductor chip comes into contact with the upper surface of the metal electrode before touching the exposed surface of the lower semiconductor chip, so static electricity flows to the metal electrode, Less likely to cause electrostatic breakdown.
【００１７】[0017]
【発明の実施の形態】以下、本発明の半導体チップ表面
露出型の樹脂封止半導体パッケージを図示の実施の形態
に基づいて説明する。なお、既に説明した部分には同一
符号を付し、重複記載を省略する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor chip surface-exposed resin-sealed semiconductor package according to the present invention will be described below with reference to the illustrated embodiment. Note that the same reference numerals are given to the already described portions, and redundant description is omitted.
【００１８】図１は本実施の形態の半導体チップ表面露
出型の樹脂封止半導体パッケージ１０における外観斜視
図、図２（Ａ）はII−II線に沿う断面図である。FIG. 1 is a perspective view of an external appearance of a resin-sealed semiconductor package 10 of the embodiment in which a semiconductor chip surface is exposed, and FIG. 2A is a cross-sectional view taken along line II-II.
【００１９】図１，図２（Ａ），（Ｂ）に示すように、
長方形の半導体チップ１０２の表面において、金属細線
１０５の接合部１０５ａが存在する左側の封止側１０２
ａのみをエポキシ等からなる封止樹脂１１により封止す
る（金属細線側を封止した樹脂を１１ａで示す）。半導
体チップ１０２の表面における手前側，右側，奥側の３
方向は、樹脂封止をしない開放側１０２ｂ，１０２ｃ，
１０２ｄに構成し、前記３方向における半導体チップ１
０２の表面の高さ１０２ｅまで、封止樹脂１１により封
止する。As shown in FIGS. 1 and 2 (A) and (B),
On the surface of the rectangular semiconductor chip 102, the left sealing side 102 where the bonding portion 105 a of the thin metal wire 105 exists.
Only a is sealed with a sealing resin 11 made of epoxy or the like (resin sealing the thin metal wire side is indicated by 11a). 3 on the front side, right side, and back side of the surface of the semiconductor chip 102
The directions are the open sides 102b, 102c,
102d, the semiconductor chip 1 in the three directions.
The surface is sealed with the sealing resin 11 up to the height 102e of the surface 02.
【００２０】また、右側の封止樹脂１１ｂの中央部に、
基板１０１のアースパターン（図示省略）に接続した金
属板等からなるアース電極１２を埋め込み、該アース電
極１２の上面は半導体チップ１０２の上面と同一面（図
２（Ａ）参照）とするか、半導体チップ１０２より高い
面（図２（Ｂ）参照）に形成する。なお、アース電極１
２と基板１０１との接続手段としては、はんだ付け，導
電性接着剤等が好適である。Further, at the center of the right sealing resin 11b,
An earth electrode 12 made of a metal plate or the like connected to an earth pattern (not shown) of the substrate 101 is embedded, and the upper surface of the earth electrode 12 is the same as the upper surface of the semiconductor chip 102 (see FIG. 2A). It is formed on a surface higher than the semiconductor chip 102 (see FIG. 2B). The ground electrode 1
As a means for connecting the substrate 2 and the substrate 101, soldering, a conductive adhesive, or the like is preferable.
【００２１】次に本実施の形態の作用を説明する。半導
体チップ１０２表面の１方向（左側）にのみ封止樹脂１
１ａが存在するため、半導体チップ１０２と封止樹脂１
１ａの接合界面の距離（長さ）が従来例に比較し短くな
る。即ち、図３に示した従来例ではロの字状に封止樹脂
１０３が形成され長いが、図１に示した本実施の形態で
封止樹脂１１の長さは従来例の約１／３である（図１と
図３の比較）。Next, the operation of the present embodiment will be described. Sealing resin 1 only in one direction (left side) on the surface of semiconductor chip 102
1a, the semiconductor chip 102 and the sealing resin 1
The distance (length) of the bonding interface 1a is shorter than in the conventional example. That is, in the conventional example shown in FIG. 3, the sealing resin 103 is formed in a square shape and is long, but in the present embodiment shown in FIG. 1, the length of the sealing resin 11 is about １ ／ of the conventional example. (Comparison of FIG. 1 and FIG. 3).
【００２２】従って、セット基板（図示省略の電子装置
の基板）への実装時のはんだ付けに伴う温度上昇があっ
ても、４方向を樹脂封止した場合（図３参照）と比較し
て、接合界面の応力の合計は低減されることになる。よ
って、接合界面の剥離発生の確率を低下させることが可
能となる。これにより半導体パッケージの信頼性を向上
させることができる。Therefore, even if the temperature rises due to soldering during mounting on a set substrate (a substrate of an electronic device not shown), compared with the case where resin sealing is performed in four directions (see FIG. 3). The total stress at the bonding interface will be reduced. Therefore, the probability of occurrence of separation at the bonding interface can be reduced. Thereby, the reliability of the semiconductor package can be improved.
【００２３】また、アース電極１２が存在することによ
り、例えば人間の指等の帯電物が半導体チップ１０２と
接触する前にアース電極１２に接触し、基板１０１のア
ースパターン（図示省略）を介して静電気をアースに流
す。これにより、半導体パッケージを静電破壊から防護
することが可能となる。Further, the presence of the ground electrode 12 allows a charged substance, such as a human finger, to come into contact with the ground electrode 12 before coming into contact with the semiconductor chip 102, and via a ground pattern (not shown) of the substrate 101. Discharge static electricity to ground. This makes it possible to protect the semiconductor package from electrostatic breakdown.
【００２４】[0024]
【発明の効果】以上説明したように本発明によれば、以
下の効果を奏することができる。 １．半導体チップ表面露出型の樹脂封止半導体パッケー
ジにおいて、半導体チップ表面の一部のみを樹脂封止す
ることで、電子装置の基板実装時におけるはんだ付けに
伴う温度上昇による熱膨張が発生した場合でも、半導体
チップと封止樹脂間の接合界面の剥離発生の確率を低く
抑制することができ、信頼性を向上させることができ
る。As described above, according to the present invention, the following effects can be obtained. 1. In a resin package of a semiconductor chip surface-exposed resin-sealed semiconductor package, only a part of the semiconductor chip surface is resin-sealed, so that even when thermal expansion occurs due to a temperature rise due to soldering when mounting an electronic device on a substrate, The probability of occurrence of peeling at the bonding interface between the semiconductor chip and the sealing resin can be suppressed low, and reliability can be improved.
【００２５】２．半導体チップ表面露出型の樹脂封止半
導体パッケージにおいて、半導体チップの上面と同一面
か、それよリ高い面にアース電極を設けることにより、
静電気による電気回路の破壊を防ぐことができ、信頼性
を向上させることができる。2. In a resin-encapsulated semiconductor package of the semiconductor chip surface exposed type, by providing the ground electrode on the same surface as the upper surface of the semiconductor chip or on a higher surface
Electric circuits can be prevented from being damaged by static electricity, and reliability can be improved.
【図１】本発明の実施の形態の外観斜視図である。FIG. 1 is an external perspective view of an embodiment of the present invention.
【図２】同実施の形態のII−II線に沿う断面図である。FIG. 2 is a sectional view taken along the line II-II of the embodiment.
【図３】従来例の外観斜視図である。FIG. 3 is an external perspective view of a conventional example.
【図４】従来例のIV−IV線に沿う断面図である。FIG. 4 is a sectional view taken along line IV-IV of a conventional example.
【図５】従来例の製造過程を示す断面図である。FIG. 5 is a sectional view showing a manufacturing process of a conventional example.
１０…半導体チップ表面露出型の樹脂封止半導体パッケ
ージ、１１…封止樹脂、１１a…金属細線側を封止した
樹脂、１１ｂ…右側の封止樹脂、１２…アース電極、１
２ａ…同一面より高いアース電極、１００…従来の半導
体チップ表面露出型の樹脂封止半導体パッケージ、１０
１…基板、１０２…半導体チップ、１０２ａ…半導体チ
ップの封止側、１０２ｂ〜１０２ｄ…半導体チップの開
放側、１０２ｅ…半導体チップ表面の高さ、１０３…封
止樹脂、１０４…導電性接着剤、１０５…金属細線、１
０５ａ…金属細線の接合部、１１０…接合界面。DESCRIPTION OF SYMBOLS 10 ... Semiconductor chip surface-exposed resin-sealed semiconductor package, 11 ... Seal resin, 11a ... Seal resin on the thin metal wire side, 11b ... Right seal resin, 12 ... Earth electrode, 1
2a: Ground electrode higher than the same plane; 100: Conventional resin-sealed semiconductor package with surface exposed type semiconductor chip;
DESCRIPTION OF SYMBOLS 1 ... board | substrate, 102 ... semiconductor chip, 102a ... sealing side of a semiconductor chip, 102b-102d ... open side of a semiconductor chip, 102e ... height of the surface of a semiconductor chip, 103 ... sealing resin, 104 ... conductive adhesive, 105 ... Metal wire, 1
05a: bonding portion of thin metal wires, 110: bonding interface.
Claims (4)
端子と前記基板とを金属線により接続すると共に、前記
金属線および半導体チップを樹脂で封止しつつ、該半導
体チップの表面を露出させてなる半導体チップ表面露出
型の樹脂封止半導体パッケージにおいて、 前記半導体チップの側面と、前記半導体チップ上の金属
線の接続箇所の周辺のみを、樹脂で封止してなることを
特徴とする半導体チップ表面露出型の樹脂封止半導体パ
ッケージ。1. A terminal of a plate-like semiconductor chip mounted on a substrate is connected to the substrate by a metal wire, and the surface of the semiconductor chip is sealed while sealing the metal wire and the semiconductor chip with a resin. An exposed semiconductor chip surface-exposed resin-encapsulated semiconductor package, characterized in that only the side surface of the semiconductor chip and the periphery of a connection point of a metal wire on the semiconductor chip are sealed with resin. Semiconductor chip surface-exposed resin-sealed semiconductor package.
脂の上面とを同一面とするか、または前記封止樹脂の上
面を前記半導体チップの露出面より高くすることを特徴
とする請求項１記載の半導体チップ表面露出型の樹脂封
止半導体パッケージ。2. The semiconductor device according to claim 1, wherein an exposed surface of the semiconductor chip is flush with an upper surface of the sealing resin, or an upper surface of the sealing resin is higher than an exposed surface of the semiconductor chip. 2. The resin packaged semiconductor package according to claim 1, wherein the semiconductor chip surface is exposed.
分に、前記基板に接続した金属電極を埋め込んだことを
特徴とする請求項１記載の半導体チップ表面露出型の樹
脂封止半導体パッケージ。3. The semiconductor chip surface-exposed type resin-sealed semiconductor package according to claim 1, wherein a metal electrode connected to said substrate is buried in a sealing resin portion other than a connection portion of said metal wire. .
極の上面とを同一面とするか、または前記金属電極の上
面を前記半導体チップの露出面より高くすることを特徴
とする請求項３記載の半導体チップ表面露出型の樹脂封
止半導体パッケージ。4. The semiconductor device according to claim 3, wherein the exposed surface of the semiconductor chip is flush with the upper surface of the metal electrode, or the upper surface of the metal electrode is higher than the exposed surface of the semiconductor chip. Semiconductor chip surface exposed type resin-encapsulated semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34916999A JP2001196505A (en) | 1999-11-05 | 1999-12-08 | Resin sealed semiconductor package with its chip surface exposed |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11-314997 | 1999-11-05 | ||
| JP31499799 | 1999-11-05 | ||
| JP34916999A JP2001196505A (en) | 1999-11-05 | 1999-12-08 | Resin sealed semiconductor package with its chip surface exposed |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001196505A true JP2001196505A (en) | 2001-07-19 |
Family
ID=26568141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34916999A Abandoned JP2001196505A (en) | 1999-11-05 | 1999-12-08 | Resin sealed semiconductor package with its chip surface exposed |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001196505A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004297071A (en) * | 2003-03-27 | 2004-10-21 | Stmicroelectronics Inc | Integrated circuit package with exposed die surfaces and auxiliary attachment |
| JP2010050488A (en) * | 2009-11-30 | 2010-03-04 | Panasonic Corp | Semiconductor device and manufacturing method thereof |
| JP2010177388A (en) * | 2009-01-29 | 2010-08-12 | Panasonic Corp | Semiconductor device, and method of manufacturing the same |
| CN112549431A (en) * | 2020-11-13 | 2021-03-26 | 深圳先进技术研究院 | Preparation method of nested structure |
| WO2023233772A1 (en) * | 2022-05-31 | 2023-12-07 | 株式会社村田製作所 | Pressure sensor device |
-
1999
- 1999-12-08 JP JP34916999A patent/JP2001196505A/en not_active Abandoned
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004297071A (en) * | 2003-03-27 | 2004-10-21 | Stmicroelectronics Inc | Integrated circuit package with exposed die surfaces and auxiliary attachment |
| JP2010177388A (en) * | 2009-01-29 | 2010-08-12 | Panasonic Corp | Semiconductor device, and method of manufacturing the same |
| JP2010050488A (en) * | 2009-11-30 | 2010-03-04 | Panasonic Corp | Semiconductor device and manufacturing method thereof |
| CN112549431A (en) * | 2020-11-13 | 2021-03-26 | 深圳先进技术研究院 | Preparation method of nested structure |
| WO2023233772A1 (en) * | 2022-05-31 | 2023-12-07 | 株式会社村田製作所 | Pressure sensor device |
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