JP2003332512A - Electronic circuit device - Google Patents

Electronic circuit device

Info

Publication number
JP2003332512A
JP2003332512A JP2002138183A JP2002138183A JP2003332512A JP 2003332512 A JP2003332512 A JP 2003332512A JP 2002138183 A JP2002138183 A JP 2002138183A JP 2002138183 A JP2002138183 A JP 2002138183A JP 2003332512 A JP2003332512 A JP 2003332512A
Authority
JP
Japan
Prior art keywords
electronic circuit
lead frame
circuit device
sealing resin
end portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002138183A
Other languages
Japanese (ja)
Inventor
Hiroaki Doi
博昭 土居
Kazuhiko Kawakami
和彦 河上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2002138183A priority Critical patent/JP2003332512A/en
Publication of JP2003332512A publication Critical patent/JP2003332512A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the generation of cracks due to exfoliation by restraining exfoliation between sealing resin and a lead frame which is caused by stress occurring in the sealing resin in a lead frame end, in an electronic circuit device. <P>SOLUTION: In the electronic circuit device, a substrate 2 on which an electronic circuit element 1 and a lead frame 3 bonded to the substrate 2 are integrally molded in a unified body by using the sealing resin 6. The main part of the end 8 of the lead frame 3 in the sealing resin 6 is formed uneven. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、電子回路装置に係
り、特に基板に接着されたリードフレームを封止樹脂で
一体成形した電子回路装置に好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device, and more particularly to an electronic circuit device in which a lead frame bonded to a substrate is integrally molded with a sealing resin.

【0002】[0002]

【従来の技術】従来の電子回路装置としては、例えば、
アサオニシムラ、スエオカワイ、ゲンムラカミ著、題
名:イフェクト オブ リード フレーム マテリアル
オンプラスチック エンキャプスレイテッド アイシ
ー パッケージ クラッキングアンダー テンパラチャ
ー サイクリング、掲載誌:アイイーイーイー トラン
ズアクションズ オン コンポーネンツ ハイブリッズ
アンド マニュファクチャリング テクノロジー、12
巻、12号、1989年12月(ASAO NISHIMURA, SUEOKAWAI, AN
D GEN MURAKAMI, 摘ffect of Lead Frame Material on
Plastic-Encapsulated IC Package Cracking Under Tem
perature Cycling・ IEEE TRANSACTIONS ON CONPONENT
S, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL.12,
NO.4, DECEMBER, 1989)に記載されたものがある。
2. Description of the Related Art As a conventional electronic circuit device, for example,
Author: Asaoni Shimura, Sueokawai, Kamimura Kami, Title: Effect of Lead Frame Material on Plastic Encapsulated Icy Package Cracking Under Temperature Cycling, Publish: IEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 12
Volume, Issue 12, December 1989 (ASAO NISHIMURA, SUEOKAWAI, AN
D GEN MURAKAMI, plucking of Lead Frame Material on
Plastic-Encapsulated IC Package Cracking Under Tem
perature Cycling ・ IEEE TRANSACTIONS ON CONPONENT
S, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL.12,
No. 4, DECEMBER, 1989).

【0003】この従来の電子回路装置を図18及び図1
9を参照しながら説明する。図18は従来の電子回路装
置の下面図、図19はその電子回路装置の断面図であ
る。なお、これらの図における符号は、後述する本発明
の実施例の符号と同一物または相当物を示す。この電子
回路装置は、シリコン製電子回路素子1と42アロイ製
リードフレーム3を接着剤12で接合し、これらをエポ
キシなどの封止樹脂6で一体成形した構造を有してい
る。これらの図にはこの電子回路装置に−55〜150
℃の温度サイクル試験を実施した場合の封止樹脂の応力
の方向を模式的に矢印で表示してある。
This conventional electronic circuit device is shown in FIG. 18 and FIG.
This will be described with reference to FIG. FIG. 18 is a bottom view of a conventional electronic circuit device, and FIG. 19 is a sectional view of the electronic circuit device. It should be noted that the reference numerals in these figures indicate the same or corresponding parts to those of the embodiments of the present invention described later. This electronic circuit device has a structure in which the electronic circuit element 1 made of silicon and the lead frame 3 made of 42 alloy are joined with an adhesive 12, and these are integrally molded with a sealing resin 6 such as epoxy. These figures show -55 to 150 in this electronic circuit device.
The direction of the stress of the sealing resin when the temperature cycle test of ℃ is carried out is schematically indicated by an arrow.

【0004】[0004]

【発明が解決しようとする課題】係る電子回路装置にお
いて、封止樹脂6は150℃の高温では軟化のために応
力がほぼ0となり、−55℃の低温ではリードフレーム
の面に平行な方向の引っ張り応力14が生じる。これは
封止樹脂6がシリコンと42アロイより大きい線膨張係
数を有し、低温では封止樹脂6が相対的に大きな収縮量
を持つためである。この応力14は図18に示されてい
るように電子回路装置の中央ではほぼ等方的であるが、
リードフレーム3の端部8ではリードフレーム3の外形
直線に垂直な応力に変化する。42アロイ製リードフレ
ーム3と封止樹脂6との接着強度はあまり高くないた
め、リードフレーム3の外形線に垂直な応力16により
はく離15が生じることがある。更に、このはく離15
がリードフレーム3と封止樹脂6との界面の広い範囲に
生じると、リードフレーム3の外形線に垂直な応力16
の集中が著しく、この応力16によりはく離した部分か
ら封止樹脂6にクラック13が生じる。温度サイクル試
験でこの応力が繰り返されると、クラック13が徐々に
進展し、封止樹脂6の表面に達する。このクラック13
は、最終的には、図19の電子回路装置の下面図に示さ
れているようにリードフレーム端部8のほぼ外形線の全
体に沿って生じる。クラック13が封止樹脂6の表面に
達すると、電子回路装置の耐湿性が損なわれ、電子回路
装置の故障の原因となる。
In the electronic circuit device according to the present invention, the encapsulating resin 6 has a stress of almost 0 due to softening at a high temperature of 150 ° C., and has a stress in a direction parallel to the surface of the lead frame at a low temperature of −55 ° C. Tensile stress 14 occurs. This is because the sealing resin 6 has a linear expansion coefficient larger than that of silicon and 42 alloy, and the sealing resin 6 has a relatively large shrinkage amount at a low temperature. This stress 14 is almost isotropic in the center of the electronic circuit device as shown in FIG.
At the end portion 8 of the lead frame 3, the stress changes into a stress perpendicular to the outline of the lead frame 3. Since the adhesive strength between the 42 alloy lead frame 3 and the sealing resin 6 is not so high, the peeling 15 may occur due to the stress 16 perpendicular to the outline of the lead frame 3. Furthermore, this peeling 15
Occurs in a wide range of the interface between the lead frame 3 and the sealing resin 6, a stress 16 perpendicular to the outline of the lead frame 3 is generated.
Is significantly concentrated, and cracks 13 are generated in the sealing resin 6 from the separated portion due to the stress 16. When this stress is repeated in the temperature cycle test, the crack 13 gradually develops and reaches the surface of the sealing resin 6. This crack 13
Finally occurs along substantially the entire outline of the lead frame end 8 as shown in the bottom view of the electronic circuit device of FIG. When the crack 13 reaches the surface of the sealing resin 6, the moisture resistance of the electronic circuit device is impaired, which causes a failure of the electronic circuit device.

【0005】本発明の目的は、リードフレーム端部の封
止樹脂に生じる応力による封止樹脂とリードフレーム間
のはく離を抑制してはく離に伴うクラックの発生を防止
できる電子回路装置を提供することにある。
An object of the present invention is to provide an electronic circuit device capable of suppressing the peeling between the sealing resin and the lead frame due to the stress generated in the sealing resin at the end of the lead frame and preventing the generation of cracks due to the peeling. It is in.

【0006】[0006]

【課題を解決するための手段】前記目的を達成するため
に本発明は、電子回路素子が搭載された基板とこの基板
に接着されたリードフレームとが封止樹脂で一体成形さ
れた電子回路装置であって、前記封止樹脂内にあるリー
ドフレームの端部の主要な部分が凹凸状に形成された構
成にしたことにある。
In order to achieve the above object, the present invention provides an electronic circuit device in which a substrate on which an electronic circuit element is mounted and a lead frame bonded to the substrate are integrally molded with a sealing resin. In addition, the main part of the end portion of the lead frame in the sealing resin is formed in a concavo-convex shape.

【0007】そして好ましくは、前記凹凸状端部は近似
的に繰り返す形状を持ち、その凹凸状端部の繰り返しの
周期長さを2Wとし、前記リードフレームの反基板側面
と前記封止樹脂の外面との距離をtとし、前記凹凸状端
部の最大点と最小点の寸法差をaとすると、W<2t及
びa>2Wの何れかまたは両方の関係が成立する前記凹
凸状端部としたことにある。
Further, preferably, the uneven end portion has an approximately repeating shape, and the repeating cycle length of the uneven end portion is set to 2 W, and the side opposite to the substrate of the lead frame and the outer surface of the sealing resin. And t is the distance between them and a is the dimensional difference between the maximum point and the minimum point of the uneven end portion, and the uneven end portion satisfies the relationship of either or both of W <2t and a> 2W. Especially.

【0008】さらに好ましくは、シリコン製電子回路素
子が搭載された基板とこの基板に接着されたアロイ製リ
ードフレームとがエポキシなどの封止樹脂で一体成形さ
れた電子回路装置であって、前記封止樹脂内にあるリー
ドフレームの両側端部が前記基板に対応する部分の全体
にわたって凹凸状に形成された構成にしたことにある。
More preferably, the electronic circuit device has a substrate on which a silicon electronic circuit element is mounted and an alloy lead frame bonded to the substrate integrally formed with a sealing resin such as epoxy, This is because both ends of the lead frame in the resin are formed in a concavo-convex shape over the entire portion corresponding to the substrate.

【0009】[0009]

【発明の実施の形態】以下、本発明の複数の実施例を図
に基づいて説明する。なお、各実施例の図における同一
符号は同一物または相当物を示す。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A plurality of embodiments of the present invention will be described below with reference to the drawings. The same reference numerals in the drawings of each embodiment indicate the same or equivalent components.

【0010】本発明の電子回路装置の第1実施例を図1
から図5を参照しながら説明する。
A first embodiment of the electronic circuit device of the present invention is shown in FIG.
From now on, description will be made with reference to FIG.

【0011】本実施例の電子回路装置は、図3から図5
に示すように、シリコン製電子回路素子1が複数個搭載
された基板2とこの基板2に接着剤12で接着された
銅、インバー、銅の積層体のリードフレーム3とがエポ
キシなどの封止樹脂6で一体成形して構成されている。
そして、基板2は外部接続端子4とアルミ細線5により
電気的に接続されている。外部接続端子は、多数設けら
れると共に、封止樹脂6の端部7から外方に突出して設
けられている。
The electronic circuit device of this embodiment is shown in FIGS.
As shown in FIG. 2, a substrate 2 on which a plurality of electronic circuit elements 1 made of silicon are mounted and a lead frame 3 of a copper, invar, or copper laminate bonded to the substrate 2 with an adhesive 12 are sealed with epoxy or the like. The resin 6 is integrally molded.
The substrate 2 is electrically connected to the external connection terminal 4 by the aluminum thin wire 5. A large number of external connection terminals are provided and are provided so as to project outward from the end portion 7 of the sealing resin 6.

【0012】リードフレーム3は、全体が長方形状に形
成され、短い辺の端部近傍に穴3aが形成される共に、
図1に示すように封止樹脂6に封止された長い辺の主要
な部分が凹凸状に形成されている。この凹凸状端部8
は、封止樹脂6内にある基板2に対応する部分の全体に
わたって形成され、近似的に繰り返す形状を有する。本
実施例では、凸部側の半円弧と凹部側の半円弧とが組み
合わされた同一の繰り返し形状となっている。なお、封
止樹脂6内に位置する穴3aにも凹凸形状が形成されて
いる。この凹凸形状の穴3aのも凹凸状端部8と同様に
はく離の抑制機能を有する。
The lead frame 3 is formed in a rectangular shape as a whole, and a hole 3a is formed in the vicinity of an end portion of a short side thereof.
As shown in FIG. 1, the major part of the long side sealed by the sealing resin 6 is formed in an uneven shape. This uneven end 8
Are formed over the entire portion of the sealing resin 6 corresponding to the substrate 2 and have an approximately repeating shape. In this embodiment, the semi-circular arc on the convex side and the semi-circular arc on the concave side are combined to have the same repeating shape. It should be noted that the hole 3 a located inside the sealing resin 6 is also formed with an uneven shape. The uneven hole 3a also has a function of suppressing peeling similarly to the uneven end portion 8.

【0013】基板2やリードフレーム3の線膨張係数は
基板2に搭載する電子回路素子1の線膨張係数に近い値
となっているため、封止樹脂6はこれらより相対的に大
きい線膨張係数を有する。係る電子回路装置に−55〜
150℃の温度サイクル試験を実施した場合の−55℃
における応力状態は図1及び図2に模式的に示す矢印の
ようになる。すなわち、封止樹脂6は150℃の高温で
は軟化するために応力がほぼ0となり、−55℃の低温
では封止樹脂6内にリードフレーム3の面に平行な方向
の引っ張り応力14、16が生じる。電子回路装置中央
に生じる応力14によりリードフレーム端部8付近に応
力16が生じるが、リードフレーム3の端部8の外形線
が凹凸状で構成されているため、応力16が広い面積に
分散して応力16の集中の程度は低減され、リードフレ
ーム3と封止樹脂6のはく離の可能性を低減する。ま
た、仮にリードフレーム3と封止樹脂6との間にはく離
が発生した場合にも、はく離に伴う封止樹脂6の応力集
中が低減するため、封止樹脂6のクラックの発生を防止
できる。
Since the linear expansion coefficient of the substrate 2 and the lead frame 3 is close to the linear expansion coefficient of the electronic circuit element 1 mounted on the substrate 2, the sealing resin 6 has a relatively large linear expansion coefficient. Have. The electronic circuit device is
-55 ° C when a 150 ° C temperature cycle test is performed
The stress state at is like the arrow schematically shown in FIGS. That is, since the encapsulating resin 6 softens at a high temperature of 150 ° C., the stress becomes almost 0, and at a low temperature of −55 ° C., tensile stresses 14 and 16 in a direction parallel to the surface of the lead frame 3 are generated in the encapsulating resin 6. Occurs. The stress 14 generated in the center of the electronic circuit device causes a stress 16 near the end portion 8 of the lead frame. However, since the outer shape of the end portion 8 of the lead frame 3 is uneven, the stress 16 is dispersed over a wide area. As a result, the degree of concentration of the stress 16 is reduced, and the possibility of peeling between the lead frame 3 and the sealing resin 6 is reduced. Further, even if peeling occurs between the lead frame 3 and the sealing resin 6, the stress concentration of the sealing resin 6 due to the peeling is reduced, so that the cracking of the sealing resin 6 can be prevented.

【0014】次に、本発明の第2実施例を図6から図1
3を参照しながら説明する。なお、この第2実施例の説
明において、上述した第1実施例と共通する部分(例え
ば電子回路装置の全体形状など)を重複して説明するこ
とは省略する。
Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. It should be noted that in the description of the second embodiment, the description common to the first embodiment described above (for example, the entire shape of the electronic circuit device) will not be repeated.

【0015】この第2実施例では、リードフレーム端部
8の凹凸形状を第1実施例より凸部を高く(換言すれ
ば、凹部を深く)すると共に、繰り返しの周期の長さを
小さくしたものである。図10から図13に示すよう
に、リードフレーム端部8の凹凸の繰り返しの周期長さ
を2W、外形線の隣り合う最大点10と最小点11の寸
法差(換言すれば、凸部の高さ)をa、リードフレーム
3の下面と封止樹脂6の下面の距離をtとして、リード
フレーム端部8の凹凸形状を具体的に説明する。
In the second embodiment, the concave and convex shape of the lead frame end portion 8 is higher than that of the first embodiment (in other words, the recess is deeper) and the length of the repeating cycle is smaller. Is. As shown in FIG. 10 to FIG. 13, the cycle length of repetition of the unevenness of the lead frame end portion 8 is 2 W, and the dimensional difference between the maximum point 10 and the minimum point 11 adjacent to each other on the outer shape line (in other words, the height of the convex portion). S) is a, and the distance between the lower surface of the lead frame 3 and the lower surface of the sealing resin 6 is t, the uneven shape of the lead frame end portion 8 will be specifically described.

【0016】封止樹脂6とリードフレーム3との間が仮
にはく離したとすると、封止樹脂6の応力16がリード
フレーム端部8の最大点10と最小点11に集中し、こ
の応力16により温度サイクルの繰り返しと共にこれら
の点を起点としてクラック13が生ずる可能性がある。
最大点10と最小点11ではほぼ同程度の大きさの応力
16が集中するため、温度サイクル試験でクラック13
は各点10、11からほぼ同時に進展することとなる。
そして、各クラック13の長さがW´に達すると、隣り
合うクラックW´が応力16の流れをさえぎるため、ク
ラック13の進展が図11に示す状態で停止する。この
クラックの長さW´は凹凸形状の繰り返し周期Wと実質
的に同一となる。
If the encapsulating resin 6 and the lead frame 3 are separated from each other, the stress 16 of the encapsulating resin 6 concentrates on the maximum point 10 and the minimum point 11 of the end portion 8 of the lead frame. The crack 13 may start from these points as the temperature cycle is repeated.
At the maximum point 10 and the minimum point 11, the stress 16 of approximately the same magnitude is concentrated, so cracks 13 are generated in the temperature cycle test.
Will progress from each point 10 and 11 almost at the same time.
Then, when the length of each crack 13 reaches W ′, the adjacent crack W ′ interrupts the flow of the stress 16, so that the progress of the crack 13 stops in the state shown in FIG. 11. The length W'of this crack is substantially the same as the cycle W of the uneven shape.

【0017】このクラック13は、クラック前縁上に各
点での応力が均一になるという力学的条件から図11に
示す封止樹脂6の厚さ方向にも進展し、図12に示すよ
うにほぼ円形状となる。このため2t>Wの関係が成立
するようにリードフレーム端部8の凹凸形状を設定すれ
ば、クラック13が封止樹脂6の表面に現れることを防
ぐことができる。このようにして、クラック13が封止
樹脂6の表面に現れないようにすることにより、電子回
路装置の耐湿性を維持することができ、信頼性の向上が
図れる。
The crack 13 also propagates in the thickness direction of the sealing resin 6 shown in FIG. 11 under the mechanical condition that the stress at each point becomes uniform on the front edge of the crack, and as shown in FIG. It becomes almost circular. Therefore, if the uneven shape of the lead frame end portion 8 is set so that the relationship of 2t> W is established, it is possible to prevent the crack 13 from appearing on the surface of the sealing resin 6. By thus preventing the cracks 13 from appearing on the surface of the sealing resin 6, the humidity resistance of the electronic circuit device can be maintained, and the reliability can be improved.

【0018】クラック13が図10の状態に進展する
と、各最大点10と最小点11から進展するクラック1
3に対する垂直応力16が消滅すると代わりに、図13
に示すようなせん断応力17が生じる。クラック13が
せん断応力17により更に進展すれば、図13に示すよ
うに隣り合うクラック13が合体する可能性がある。こ
のようにクラック13が更に進展して合体するか合体し
ないかは、寸法Wと寸法aとの関係により決まる。この
条件を以下に説明する。
When the crack 13 propagates to the state shown in FIG. 10, the crack 1 propagates from each maximum point 10 and minimum point 11.
Instead of the normal stress 16 for 3 disappearing, FIG.
Shear stress 17 as shown in FIG. If the crack 13 further develops due to the shear stress 17, the adjacent cracks 13 may merge as shown in FIG. In this way, whether the crack 13 further develops and merges or does not merge is determined by the relationship between the dimension W and the dimension a. This condition will be described below.

【0019】封止樹脂6の引っ張り強度をσfとする。
クラック13を生じる時の幅W´当たりの力Fは次の式
(1)で表される。
Let the tensile strength of the sealing resin 6 be σf.
The force F per width W ′ when the crack 13 is generated is calculated by the following formula.
It is represented by (1).

【0020】F=Wtσf ……(1) 図13における間隔aの間の力Fによるせん断応力τは
次の式(2)で表される。
F = Wtσf (1) The shear stress τ due to the force F during the interval a in FIG. 13 is expressed by the following equation (2).

【0021】τ=F/(at) ……(2) 封止樹脂6のせん断強度τfと引っ張り強度σfの関係
は封止樹脂材料により異なるが、普通τfはσfの1/
2以上の値であるので、次の式(3)で表される。
Τ = F / (at) (2) The relationship between the shear strength τf and the tensile strength σf of the sealing resin 6 differs depending on the sealing resin material, but normally τf is 1 / of σf.
Since the value is 2 or more, it is represented by the following equation (3).

【0022】τf≧σf/2 ……(3) ここで、クラック13が進展しない条件は式(2)のせん
断力τがτf以下になることであるので、式(2)、(3)
を用いることにより、この条件は次の式(4)と表され
る。
Τf ≧ σf / 2 (3) Here, since the condition that the crack 13 does not propagate is that the shearing force τ of the equation (2) becomes τf or less, the equations (2) and (3)
By using, this condition is expressed by the following equation (4).

【0023】F/(ta)≦σf/2 ……(4) 更に式(1)を用いて表すと、次の式(5)が導かれる。F / (ta) ≦ σf / 2 (4) Further, using the equation (1), the following equation (5) is derived.

【0024】a≧2W ……(5) 結局、クラック13がせん断応力17により更に進展し
て隣り合うクラックが合体することを防止する条件は式
(5)で表される。
A ≧ 2W (5) After all, the condition for preventing the crack 13 from further advancing due to the shear stress 17 and the adjoining cracks coalescing is expressed by the formula
It is represented by (5).

【0025】以上を纏めると、リードフレーム3の外形
線の主要な部分が近似的に繰り返し形状を持ち、その繰
り返しの周期長さを2W、リードフレーム3の下面と電
子装置の下面の距離をtとすると、W<2tの関係が成
立し、外形線の隣り合う最大点と最小点の寸法差をaと
すると、a>2Wの関係が成立すればリードフレーム端
部8の封止樹脂6に生じるクラック13の進展を防いで
封止樹脂6の表面に達することを防止できる。
In summary, the main part of the outline of the lead frame 3 has an approximately repeating shape, the cycle length of the repetition is 2 W, and the distance between the lower surface of the lead frame 3 and the lower surface of the electronic device is t. Then, the relationship of W <2t is established, and assuming that the dimensional difference between the maximum point and the minimum point adjacent to each other on the outline is a, if the relationship of a> 2W is established, the sealing resin 6 of the end portion 8 of the lead frame is It is possible to prevent the crack 13 from developing and prevent the crack 13 from reaching the surface of the sealing resin 6.

【0026】次に、本発明の第3実施例を図14及び図
15を参照しながら説明する。なお、この第3実施例の
説明において、上述した第1実施例と共通する部分(例
えば電子回路装置の全体形状など)を重複して説明する
ことは省略する。
Next, a third embodiment of the present invention will be described with reference to FIGS. 14 and 15. It should be noted that in the description of the third embodiment, duplicated description of the portions common to the above-described first embodiment (for example, the overall shape of the electronic circuit device) will be omitted.

【0027】この第3実施例では、リードフレーム端部
8の外形線の凹凸形状が折れ線で構成されている。この
第3実施例でもリードフレーム端部8における応力を低
減できるため、はく離に伴う封止樹脂6の応力集中によ
る封止樹脂6のクラック13の発生を防止できる。
In the third embodiment, the irregular shape of the outline of the lead frame end portion 8 is formed by a polygonal line. Since the stress at the lead frame end portion 8 can be reduced also in the third embodiment, it is possible to prevent the occurrence of cracks 13 in the sealing resin 6 due to stress concentration of the sealing resin 6 due to peeling.

【0028】次に、本発明の第4実施例を図16及び図
17を参照しながら説明する。なお、この第4実施例の
説明において、上述した第1実施例と共通する部分(例
えばこの第4実施例では、リードフレーム3の外形線の
凹凸形状が曲線で構成されている。この第4実施例では
リードフレーム端部8が封止樹脂6と組み合っているた
め、上述した第1から第3実施例に比べ更にリードフレ
ーム端部8付近の封止樹脂6の応力を低減できる。これ
によって、はく離の防止効果が高く、はく離が発生した
場合にもはく離に伴う封止樹脂6の応力集中による封止
樹脂6のクラックの発生の防止効果が高い。
Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the description of the fourth embodiment, a portion common to the above-described first embodiment (for example, in the fourth embodiment, the uneven shape of the outline of the lead frame 3 is formed by a curved line. In the embodiment, since the lead frame end portion 8 is combined with the sealing resin 6, the stress of the sealing resin 6 near the lead frame end portion 8 can be further reduced as compared with the above-described first to third embodiments. The effect of preventing peeling is high, and even when peeling occurs, the effect of preventing cracks in the sealing resin 6 due to stress concentration of the sealing resin 6 accompanying peeling is high.

【0029】[0029]

【発明の効果】上述した実施例の説明から明らかなよう
に、本発明によれば、リードフレーム端部の封止樹脂に
生じる応力による封止樹脂とリードフレーム間のはく離
を抑制してはく離に伴うクラックの発生を防止できる電
子回路装置を得ることができる。
As is apparent from the above description of the embodiments, according to the present invention, the peeling between the sealing resin and the lead frame due to the stress generated in the sealing resin at the end portion of the lead frame is suppressed to prevent the peeling. It is possible to obtain an electronic circuit device that can prevent the occurrence of cracks.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例に係る電子回路装置の応力
状態を模式的に表示した下面図である。
FIG. 1 is a bottom view schematically showing a stress state of an electronic circuit device according to a first embodiment of the present invention.

【図2】図1の電子回路装置の応力状態を模式的に表示
した正面図である。
FIG. 2 is a front view schematically showing a stress state of the electronic circuit device of FIG.

【図3】図1の電子回路装置の平面図である。3 is a plan view of the electronic circuit device of FIG. 1. FIG.

【図4】図1の電子回路装置の正面図である。FIG. 4 is a front view of the electronic circuit device of FIG.

【図5】図1の電子回路装置の側面図である。5 is a side view of the electronic circuit device of FIG. 1. FIG.

【図6】本発明の第2実施例に係る電子回路装置の平面
図である。
FIG. 6 is a plan view of an electronic circuit device according to a second embodiment of the present invention.

【図7】図6の電子回路装置の正面図である。FIG. 7 is a front view of the electronic circuit device of FIG.

【図8】図6の電子回路装置の側面図である。8 is a side view of the electronic circuit device of FIG.

【図9】図6の電子回路装置の下面図である。9 is a bottom view of the electronic circuit device of FIG. 6. FIG.

【図10】図6の電子回路装置の一部拡大下面図であ
る。
10 is a partially enlarged bottom view of the electronic circuit device of FIG.

【図11】図6のA−A断面図である。11 is a cross-sectional view taken along the line AA of FIG.

【図12】図6の電子回路装置の側面図である。12 is a side view of the electronic circuit device of FIG.

【図13】図6の電子回路装置の側面図である。13 is a side view of the electronic circuit device of FIG.

【図14】本発明の第3実施例に係る電子回路装置の下
面図である。
FIG. 14 is a bottom view of the electronic circuit device according to the third embodiment of the present invention.

【図15】図14の電子回路装置の正面図である。FIG. 15 is a front view of the electronic circuit device of FIG.

【図16】本発明の第4実施例に係る電子回路装置の下
面図である。
FIG. 16 is a bottom view of the electronic circuit device according to the fourth embodiment of the present invention.

【図17】図16の電子回路装置の正面図である。FIG. 17 is a front view of the electronic circuit device of FIG. 16.

【図18】従来の電子回路装置の平面図である。FIG. 18 is a plan view of a conventional electronic circuit device.

【図19】図18の電子回路装置の縦断面図である。19 is a vertical cross-sectional view of the electronic circuit device of FIG.

【符号の説明】[Explanation of symbols]

1…電子回路素子、2…基板、3…リードフレーム、4
…外部接続端子、5…アルミ細線、6…封止樹脂、7…
封止樹脂端部、8…リードフレーム端部、9…基板端
部、10…最大点、11…最小点、12…接着剤、13
…クラック、14…応力、15…応力、16…応力、1
7…せん断応力。
1 ... Electronic circuit element, 2 ... Substrate, 3 ... Lead frame, 4
… External connection terminals, 5… Aluminum fine wires, 6… Sealing resin, 7…
End of sealing resin, 8 ... End of lead frame, 9 ... End of substrate, 10 ... Maximum point, 11 ... Minimum point, 12 ... Adhesive agent, 13
… Crack, 14… Stress, 15… Stress, 16… Stress, 1
7 ... Shear stress.

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】電子回路素子が搭載された基板とこの基板
に接着されたリードフレームとが封止樹脂で一体成形さ
れた電子回路装置であって、 前記封止樹脂内にあるリードフレームの端部の主要な部
分が凹凸状に形成されたことを特徴とした電子回路装
置。
1. An electronic circuit device in which a substrate on which an electronic circuit element is mounted and a lead frame adhered to the substrate are integrally molded with a sealing resin, and an end of the lead frame in the sealing resin. An electronic circuit device characterized in that main portions of the parts are formed in an uneven shape.
【請求項2】請求項1において、前記凹凸状端部は近似
的に繰り返す形状を持ち、その凹凸形状の繰り返しの周
期長さを2Wとし、前記リードフレームの反基板側面と
前記封止樹脂の外面との距離をtとすると、W<2tの
関係が成立する前記凹凸状端部としたことを特徴とする
電子回路装置。
2. The concave-convex end portion has an approximately repeating shape, and the cycle length of the repeating concave-convex shape is 2 W, and the opposite side surface of the lead frame and the sealing resin are formed. An electronic circuit device characterized in that the concave and convex end portions satisfy a relationship of W <2t, where t is a distance from the outer surface.
【請求項3】請求項1において、前記凹凸状端部は近似
的に繰り返す形状を持ち、その凹凸状端部の繰り返しの
周期長さを2Wとし、前記凹凸状端部の最大点と最小点
の寸法差をaとすると、a>2Wの関係が成立する前記
凹凸状端部としたことを特徴とする電子回路装置。
3. The convex-concave end portion has an approximately repeating shape, and the cycle length of repetition of the convex-concave end portion is 2 W, and the maximum point and the minimum point of the concave-convex end portion are defined as follows. The electronic circuit device is characterized in that the concave-convex end portions satisfy the relationship of a> 2W, where a is the dimensional difference.
【請求項4】請求項1において、前記凹凸状端部は近似
的に繰り返す形状を持ち、その凹凸状端部の繰り返しの
周期長さを2Wとし、前記リードフレームの反基板側面
と前記封止樹脂の外面との距離をtとし、前記凹凸状端
部の最大点と最小点の寸法差をaとすると、W<2t及
びa>2Wの関係が両立する前記凹凸状端部としたこと
を特徴とする電子回路装置。
4. The concave-convex end portion has an approximately repeating shape, and the repetition period length of the concave-convex end portion is 2 W, and the side opposite to the substrate of the lead frame and the sealing member are formed. When the distance from the outer surface of the resin is t and the dimensional difference between the maximum point and the minimum point of the uneven end portion is a, the uneven end portion satisfying the relations of W <2t and a> 2W is satisfied. Characteristic electronic circuit device.
【請求項5】シリコン製電子回路素子が搭載された基板
とこの基板に接着された銅、インバー、銅の積層体のリ
ードフレームとがエポキシなどの封止樹脂で一体成形さ
れた電子回路装置であって、 前記封止樹脂内にあるリードフレームの両側端部が前記
基板に対応する部分の全体にわたって凹凸状に形成され
たことを特徴とした電子回路装置。
5. An electronic circuit device in which a substrate on which an electronic circuit element made of silicon is mounted and a lead frame of a laminated body of copper, Invar, and copper adhered to this substrate are integrally molded with a sealing resin such as epoxy. The electronic circuit device is characterized in that both end portions of the lead frame in the sealing resin are formed in a concavo-convex shape over the entire portion corresponding to the substrate.
JP2002138183A 2002-05-14 2002-05-14 Electronic circuit device Pending JP2003332512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002138183A JP2003332512A (en) 2002-05-14 2002-05-14 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002138183A JP2003332512A (en) 2002-05-14 2002-05-14 Electronic circuit device

Publications (1)

Publication Number Publication Date
JP2003332512A true JP2003332512A (en) 2003-11-21

Family

ID=29699695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002138183A Pending JP2003332512A (en) 2002-05-14 2002-05-14 Electronic circuit device

Country Status (1)

Country Link
JP (1) JP2003332512A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351755A (en) * 2005-06-15 2006-12-28 Renesas Technology Corp Semiconductor device
CN108695273A (en) * 2017-07-17 2018-10-23 睿力集成电路有限公司 Window-type ball grid array package assembling
WO2019176783A1 (en) * 2018-03-12 2019-09-19 ローム株式会社 Semiconductor device, and mounting structure for semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351755A (en) * 2005-06-15 2006-12-28 Renesas Technology Corp Semiconductor device
CN108695273A (en) * 2017-07-17 2018-10-23 睿力集成电路有限公司 Window-type ball grid array package assembling
CN108695273B (en) * 2017-07-17 2020-05-26 长鑫存储技术有限公司 Window type ball grid array packaging assembly
WO2019176783A1 (en) * 2018-03-12 2019-09-19 ローム株式会社 Semiconductor device, and mounting structure for semiconductor device
CN111868919A (en) * 2018-03-12 2020-10-30 罗姆股份有限公司 Semiconductor device and mounting structure of semiconductor device
JPWO2019176783A1 (en) * 2018-03-12 2021-02-25 ローム株式会社 Semiconductor devices and mounting structures for semiconductor devices
US11322459B2 (en) 2018-03-12 2022-05-03 Rohm Co., Ltd. Lead of semiconductor device having a side surface with a plurality of recess areas
JP7257380B2 (en) 2018-03-12 2023-04-13 ローム株式会社 Semiconductor device and mounting structure of semiconductor device
CN111868919B (en) * 2018-03-12 2024-02-27 罗姆股份有限公司 Semiconductor device and mounting structure of semiconductor device

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