JP7017093B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP7017093B2
JP7017093B2 JP2018033471A JP2018033471A JP7017093B2 JP 7017093 B2 JP7017093 B2 JP 7017093B2 JP 2018033471 A JP2018033471 A JP 2018033471A JP 2018033471 A JP2018033471 A JP 2018033471A JP 7017093 B2 JP7017093 B2 JP 7017093B2
Authority
JP
Japan
Prior art keywords
heat sink
resin layer
insulating resin
semiconductor chip
bonding tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018033471A
Other languages
Japanese (ja)
Other versions
JP2019149468A (en
Inventor
真悟 岩崎
智弘 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2018033471A priority Critical patent/JP7017093B2/en
Publication of JP2019149468A publication Critical patent/JP2019149468A/en
Application granted granted Critical
Publication of JP7017093B2 publication Critical patent/JP7017093B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本明細書に開示の技術は、半導体装置に関する。 The techniques disclosed herein relate to semiconductor devices.

特許文献１に開示の半導体装置は、一対の放熱板とその間に配置された半導体チップとを備えている。半導体チップは、各放熱板に導電部材等を介して接続されている。また、半導体チップの周囲に絶縁樹脂層が配置されている。絶縁樹脂層は、半導体チップを封止している。絶縁樹脂は、一対の放熱板の対向する表面に接している。 The semiconductor device disclosed in Patent Document 1 includes a pair of heat sinks and a semiconductor chip arranged between them. The semiconductor chip is connected to each heat sink via a conductive member or the like. Further, an insulating resin layer is arranged around the semiconductor chip. The insulating resin layer seals the semiconductor chip. The insulating resin is in contact with the opposing surfaces of the pair of heat sinks.

特開２０１２－２３５０８１号公報Japanese Unexamined Patent Publication No. 2012-235081

半導体装置の使用時に、半導体チップが繰り返し発熱する。このため、半導体装置の温度は繰り返し変動する。半導体装置の温度が低下すると、絶縁樹脂層と半導体チップが収縮する。このとき、絶縁樹脂層が半導体チップよりも収縮する。半導体チップと絶縁樹脂層の収縮量に差があるため、絶縁樹脂層と各放熱板の接触面に高い引張応力が加わる。引張応力によって、絶縁樹脂層が放熱板から剥離するおそれがある。絶縁樹脂層が放熱板から剥離すると、その剥離部に沿って水分が進入し易くなるため、半導体チップの信頼性が低下する。この問題に対し、本明細書では、絶縁樹脂層が放熱板から剥離し難い半導体装置を提案する。 When using a semiconductor device, the semiconductor chip repeatedly generates heat. Therefore, the temperature of the semiconductor device fluctuates repeatedly. When the temperature of the semiconductor device decreases, the insulating resin layer and the semiconductor chip shrink. At this time, the insulating resin layer shrinks more than the semiconductor chip. Since there is a difference in the amount of shrinkage between the semiconductor chip and the insulating resin layer, high tensile stress is applied to the contact surface between the insulating resin layer and each heat sink. The tensile stress may cause the insulating resin layer to peel off from the heat sink. When the insulating resin layer is peeled off from the heat sink, moisture easily enters along the peeled portion, so that the reliability of the semiconductor chip is lowered. To solve this problem, the present specification proposes a semiconductor device in which the insulating resin layer is difficult to peel off from the heat sink.

本明細書が開示する半導体装置は、第１表面を有する第１放熱板と、前記第１表面に対向する第２表面を有する第２放熱板と、前記第１表面の一部と前記第２表面の一部に接続されている半導体チップと、前記第１表面にループ状にボンディングされているとともに前記半導体チップの外周縁に沿って伸びるボンディングテープと、前記第１表面と前記第２表面に接しているとともに前記半導体チップと前記ボンディングテープを封止する絶縁樹脂層を有する。前記絶縁樹脂層の前記ボンディングテープに対する密着強度が、前記絶縁樹脂層の前記第１放熱板及び前記第２放熱板に対する密着強度よりも低い。 The semiconductor device disclosed in the present specification includes a first heat radiating plate having a first surface, a second heat radiating plate having a second surface facing the first surface, a part of the first surface, and the second. A semiconductor chip connected to a part of the surface, a bonding tape bonded to the first surface in a loop shape and extending along the outer peripheral edge of the semiconductor chip, and the first surface and the second surface. It has an insulating resin layer that is in contact with the semiconductor chip and seals the bonding tape. The adhesive strength of the insulating resin layer to the bonding tape is lower than the adhesive strength of the insulating resin layer to the first heat sink and the second heat sink.

この半導体装置の温度が低下すると、絶縁樹脂層と各放熱板の接触面に引張応力が加わるだけでなく、絶縁樹脂層とボンディングテープの界面にも引張応力が加わる。絶縁樹脂層のボンディングテープに対する密着強度が低いので、絶縁樹脂層がボンディングテープから剥離し易い。このため、ボンディングテープが各放熱板よりも先に絶縁樹脂層から剥離する。ボンディングテープが絶縁樹脂層から剥離すると、その剥離部の周辺で引張応力が緩和される。これによって、絶縁樹脂層が各放熱板から剥離することが防止される。また、ボンディングテープのループ状の部分は第１表面から浮いているので、ループ状の部分でボンディングテープが絶縁樹脂層から剥離しても、その剥離部の周囲は絶縁樹脂層に囲まれている。このため、この剥離部は、水分の進入経路とはならず、半導体チップの信頼性に影響を与えない。以上に説明したように、この半導体装置によれば、半導体チップの高い信頼性を実現することができる。 When the temperature of this semiconductor device decreases, not only tensile stress is applied to the contact surface between the insulating resin layer and each heat sink, but also tensile stress is applied to the interface between the insulating resin layer and the bonding tape. Since the adhesive strength of the insulating resin layer to the bonding tape is low, the insulating resin layer is easily peeled off from the bonding tape. Therefore, the bonding tape is peeled off from the insulating resin layer before each heat sink. When the bonding tape is peeled from the insulating resin layer, the tensile stress is relaxed around the peeled portion. This prevents the insulating resin layer from peeling off from each heat sink. Further, since the loop-shaped portion of the bonding tape is floating from the first surface, even if the bonding tape is peeled from the insulating resin layer at the loop-shaped portion, the peeled portion is surrounded by the insulating resin layer. .. Therefore, this peeled portion does not serve as an entry path for moisture and does not affect the reliability of the semiconductor chip. As described above, according to this semiconductor device, high reliability of the semiconductor chip can be realized.

半導体装置１０の断面図（図２のＩ－Ｉ線における断面図）。Sectional drawing of the semiconductor device 10 (cross-sectional view taken along line I-I of FIG. 2). 半導体チップ１４と下部放熱板１２の平面図。Top view of the semiconductor chip 14 and the lower heat sink 12. 図２のＩＩＩ－ＩＩＩ線における断面図。FIG. 2 is a cross-sectional view taken along the line III-III of FIG. 図２のＩＶ－ＩＶ線における断面図。FIG. 2 is a cross-sectional view taken along the line IV-IV of FIG.

図１に示す実施形態の半導体装置１０は、下部放熱板１２、半導体チップ１４、金属ブロック１６、上部放熱板１８、複数の信号端子２０、及び、絶縁樹脂層２２を有している。 The semiconductor device 10 of the embodiment shown in FIG. 1 has a lower heat sink 12, a semiconductor chip 14, a metal block 16, an upper heat sink 18, a plurality of signal terminals 20, and an insulating resin layer 22.

下部放熱板１２は、銅等の金属により構成されている。 The lower heat sink 12 is made of a metal such as copper.

半導体チップ１４は、下部放熱板１２上に配置されている。半導体チップ１４は、半導体基板１４ａと、上部電極１４ｂと、複数の信号電極１４ｃと、下部電極１４ｄを有している。図２に示すように、上部電極１４ｂは、半導体基板１４ａの上面に配置されている。上部電極１４ｂは、半導体基板１４ａの上面の大部分を覆っている。複数の信号電極１４ｃは、半導体基板１４ａの上面に配置されている。複数の信号電極１４ｃは、上部電極１４ｂの隣に設けられている。下部電極１４ｄは、半導体基板１４ａの下面に配置されている。半導体チップ１４の下部電極１４ｄは、はんだ層３０によって下部放熱板１２の上面の中央部に接続されている。 The semiconductor chip 14 is arranged on the lower heat sink 12. The semiconductor chip 14 has a semiconductor substrate 14a, an upper electrode 14b, a plurality of signal electrodes 14c, and a lower electrode 14d. As shown in FIG. 2, the upper electrode 14b is arranged on the upper surface of the semiconductor substrate 14a. The upper electrode 14b covers most of the upper surface of the semiconductor substrate 14a. The plurality of signal electrodes 14c are arranged on the upper surface of the semiconductor substrate 14a. The plurality of signal electrodes 14c are provided next to the upper electrode 14b. The lower electrode 14d is arranged on the lower surface of the semiconductor substrate 14a. The lower electrode 14d of the semiconductor chip 14 is connected to the central portion of the upper surface of the lower heat sink 12 by the solder layer 30.

金属ブロック１６は、銅等の金属により構成されている。金属ブロック１６は、半導体チップ１４の上部電極１４ｂ上に配置されている。金属ブロック１６の下面は、はんだ層３２によって上部電極１４ｂに接続されている。 The metal block 16 is made of a metal such as copper. The metal block 16 is arranged on the upper electrode 14b of the semiconductor chip 14. The lower surface of the metal block 16 is connected to the upper electrode 14b by the solder layer 32.

上部放熱板１８は、銅等の金属により構成されている。上部放熱板１８は、金属ブロック１６上に配置されている。上部放熱板１８の下面の中央部は、はんだ層３４によって金属ブロック１６の上面に接続されている。 The upper heat sink 18 is made of a metal such as copper. The upper heat sink 18 is arranged on the metal block 16. The central portion of the lower surface of the upper heat sink 18 is connected to the upper surface of the metal block 16 by the solder layer 34.

下部放熱板１２の面積と上部放熱板１８の面積は、半導体チップ１４の面積よりも大きい。したがって、半導体チップ１４の周囲において、下部放熱板１２の上面と上部放熱板１８の上面が対向している。 The area of the lower heat sink 12 and the area of the upper heat sink 18 are larger than the area of the semiconductor chip 14. Therefore, the upper surface of the lower heat sink 12 and the upper surface of the upper heat sink 18 face each other around the semiconductor chip 14.

図１、２に示すように、複数の信号端子２０は、下部放熱板１２の側方に配置されている。各信号端子２０は、ボンディングワイヤ３８によって、対応する信号電極１４ｃに接続されている。 As shown in FIGS. 1 and 2, a plurality of signal terminals 20 are arranged on the side of the lower heat sink 12. Each signal terminal 20 is connected to the corresponding signal electrode 14c by a bonding wire 38.

図１に示すように、下部放熱板１２と上部放熱板１８の間に、ボンディングテープ４０が配置されている。ボンディングテープ４０は、下部放熱板１２及び上部放熱板１８よりも絶縁樹脂層２２に対する密着強度が低い金属によって構成されたテープである。すなわち、ボンディングテープ４０は、下部放熱板１２及び上部放熱板１８よりも絶縁樹脂層２２から剥離し易い。本実施形態では、ボンディングテープ４０は、アルミニウムによって構成されている。図２に示すように、半導体チップ１４の外周縁に沿って、４つのボンディングテープ４０ａ～４０ｄが配置されている。４つのボンディングテープ４０ａ～４０ｄによって、半導体チップ１４の周囲全体が囲まれている。図３は、ボンディングテープ４０ｂの断面を示している。ボンディングテープ４０ｂは、単一ループにより構成されており、その両端部で下部放熱板１２の上面にボンディングされている。ボンディングテープ４０ａ、４０ｃも、ボンディングテープ４０ｂと同様に、単一ループにより構成されている。図４に示すように、ボンディングテープ４０ｄは、３つのループにより構成されており、４か所で下部放熱板１２の上面にボンディングされている。このため、ボンディングテープ４０ｄのループの高さは、ボンディングテープ４０ａ～４０ｃのループの高さよりも低い。ボンディングテープ４０ｄのループの高さが低いことで、ボンディングテープ４０ｄとボンディングワイヤ３８との間の距離が確保されている。 As shown in FIG. 1, a bonding tape 40 is arranged between the lower heat sink 12 and the upper heat sink 18. The bonding tape 40 is a tape made of a metal having a lower adhesion strength to the insulating resin layer 22 than the lower heat sink 12 and the upper heat sink 18. That is, the bonding tape 40 is easier to peel off from the insulating resin layer 22 than the lower heat sink 12 and the upper heat sink 18. In this embodiment, the bonding tape 40 is made of aluminum. As shown in FIG. 2, four bonding tapes 40a to 40d are arranged along the outer peripheral edge of the semiconductor chip 14. The entire circumference of the semiconductor chip 14 is surrounded by the four bonding tapes 40a to 40d. FIG. 3 shows a cross section of the bonding tape 40b. The bonding tape 40b is composed of a single loop, and is bonded to the upper surface of the lower heat sink 12 at both ends thereof. Like the bonding tape 40b, the bonding tapes 40a and 40c are also composed of a single loop. As shown in FIG. 4, the bonding tape 40d is composed of three loops, and is bonded to the upper surface of the lower heat sink 12 at four points. Therefore, the height of the loop of the bonding tape 40d is lower than the height of the loop of the bonding tapes 40a to 40c. The low loop height of the bonding tape 40d ensures a distance between the bonding tape 40d and the bonding wire 38.

絶縁樹脂層２２は、下部放熱板１２と上部放熱板１８の間に設けられている。絶縁樹脂層２２は、半導体チップ１４、金属ブロック１６、及び、ボンディングテープ４０を封止している。また、絶縁樹脂層２２は、下部放熱板１２の上面と上部放熱板１８の下面に密着している。 The insulating resin layer 22 is provided between the lower heat sink 12 and the upper heat sink 18. The insulating resin layer 22 seals the semiconductor chip 14, the metal block 16, and the bonding tape 40. Further, the insulating resin layer 22 is in close contact with the upper surface of the lower heat radiating plate 12 and the lower surface of the upper heat radiating plate 18.

絶縁樹脂層２２を形成するときには、溶融状態の樹脂が下部放熱板１２と上部放熱板１８の間に充填される。その後、樹脂が冷却されると、樹脂が硬化して絶縁樹脂層２２となる。絶縁樹脂層２２が冷却されるときに、絶縁樹脂層２２が収縮する。このとき、半導体チップ１４と金属ブロック１６も収縮するが、これらは絶縁樹脂層２２ほど収縮しない。このため、絶縁樹脂層２２と下部放熱板１２の間の接着面、及び、絶縁樹脂層２２と上部放熱板１８の間の接着面に、引張応力が加わる。また、半導体装置１０の使用時に、半導体チップ１４に繰り返し電流が流れ、半導体チップ１４が繰り返し発熱する。その結果、絶縁樹脂層２２が膨張と収縮を繰り返す。その結果、絶縁樹脂層２２と下部放熱板１２の間の接着面、及び、絶縁樹脂層２２と上部放熱板１８の間の接着面に加わる引張応力が繰り返し変化する。引張応力によって絶縁樹脂層２２が下部放熱板１２及び上部放熱板１８から剥離すると、半導体チップ１４の信頼性に問題が生じる。 When the insulating resin layer 22 is formed, the molten resin is filled between the lower heat sink 12 and the upper heat sink 18. After that, when the resin is cooled, the resin is cured to form the insulating resin layer 22. When the insulating resin layer 22 is cooled, the insulating resin layer 22 shrinks. At this time, the semiconductor chip 14 and the metal block 16 also shrink, but they do not shrink as much as the insulating resin layer 22. Therefore, tensile stress is applied to the adhesive surface between the insulating resin layer 22 and the lower heat sink 12 and the adhesive surface between the insulating resin layer 22 and the upper heat sink 18. Further, when the semiconductor device 10 is used, a current repeatedly flows through the semiconductor chip 14, and the semiconductor chip 14 repeatedly generates heat. As a result, the insulating resin layer 22 repeats expansion and contraction. As a result, the tensile stress applied to the adhesive surface between the insulating resin layer 22 and the lower heat sink 12 and the adhesive surface between the insulating resin layer 22 and the upper heat sink 18 repeatedly changes. When the insulating resin layer 22 is peeled from the lower heat sink 12 and the upper heat sink 18 due to tensile stress, a problem arises in the reliability of the semiconductor chip 14.

これに対し、本実施形態の半導体装置１０では、絶縁樹脂層２２と下部放熱板１２の間の接着面、及び、絶縁樹脂層２２と上部放熱板１８の間の接着面に加わる引張応力と略同じ引張応力が、絶縁樹脂層２２とボンディングテープ４０の接着面にも加わる。上述したように、ボンディングテープ４０は、下部放熱板１２及び上部放熱板１８よりも絶縁樹脂層２２から剥離し易い。したがって、絶縁樹脂層２２は、下部放熱板１２及び上部放熱板１８から剥離するよりも前に、ボンディングテープ４０から剥離する。ボンディングテープ４０の大部分はループ部により構成されているので、絶縁樹脂層２２はボンディングテープ４０のループ部から剥離する。例えば、絶縁樹脂層２２は、ボンディングテープ４０の上面または下面から剥離する。絶縁樹脂層２２がボンディングテープ４０から剥離すると、その剥離部の周囲で引張応力が緩和される。特に、剥離部に対向する位置において、下部放熱板１２の上面及び上部放熱板１８の下面に加わる引張応力が緩和される。このため、絶縁樹脂層２２が下部放熱板１２の上面及び上部放熱板１８の下面から剥離することが抑制される。したがって、下部放熱板１２または上部放熱板１８に沿って剥離が進行し、剥離部によって半導体チップ１４と外部とが接続されることが抑制される。また、ボンディングテープ４０のループ部は下部放熱板１２から浮いているので、ループ部はその周囲を絶縁樹脂層２２で囲まれている。このため、ボンディングテープ４０のループ部で剥離が生じても、半導体チップ１４の信頼性に影響はない。したがって、この半導体装置１０は、高い信頼性を有している。 On the other hand, in the semiconductor device 10 of the present embodiment, the tensile stress applied to the adhesive surface between the insulating resin layer 22 and the lower heat radiating plate 12 and the adhesive surface between the insulating resin layer 22 and the upper heat radiating plate 18 is abbreviated. The same tensile stress is applied to the adhesive surface between the insulating resin layer 22 and the bonding tape 40. As described above, the bonding tape 40 is easier to peel off from the insulating resin layer 22 than the lower heat radiating plate 12 and the upper heat radiating plate 18. Therefore, the insulating resin layer 22 is peeled from the bonding tape 40 before being peeled from the lower heat sink 12 and the upper heat sink 18. Since most of the bonding tape 40 is composed of a loop portion, the insulating resin layer 22 is peeled off from the loop portion of the bonding tape 40. For example, the insulating resin layer 22 is peeled off from the upper surface or the lower surface of the bonding tape 40. When the insulating resin layer 22 is peeled from the bonding tape 40, the tensile stress is relaxed around the peeled portion. In particular, the tensile stress applied to the upper surface of the lower heat sink 12 and the lower surface of the upper heat sink 18 is relaxed at the position facing the peeled portion. Therefore, the insulating resin layer 22 is prevented from peeling from the upper surface of the lower heat sink 12 and the lower surface of the upper heat sink 18. Therefore, peeling proceeds along the lower heat sink 12 or the upper heat sink 18, and the peeling portion suppresses the connection between the semiconductor chip 14 and the outside. Further, since the loop portion of the bonding tape 40 floats from the lower heat radiating plate 12, the loop portion is surrounded by the insulating resin layer 22. Therefore, even if the loop portion of the bonding tape 40 is peeled off, the reliability of the semiconductor chip 14 is not affected. Therefore, the semiconductor device 10 has high reliability.

なお、ボンディングテープ４０のループ部で剥離することが好ましいため、ボンディングテープ４０が下部放熱板１２にボンディングされている箇所は少ない方が好ましい。したがって、ボンディングワイヤ３８が設けられていない箇所では、図３に示すように、ボンディングテープ４０が両端でのみボンディングされていることが好ましい。また、ボンディングワイヤ３８が設けられている箇所では、図４に示すように、ループを低くするために、両端以外の部分でもボンディングテープ４０がボンディングされている。しかしながら、図２に示すように、半導体チップ１４と下部放熱板１２の端面の間の幅は、ボンディングワイヤ３８が設けられている箇所（すなわち、幅Ｗ１）で、ボンディングワイヤ３８が設けられていない箇所（すなわち、幅Ｗ２）よりも広い。したがって、ボンディングワイヤ３８が設けられている箇所では、絶縁樹脂層２２が下部放熱板１２から剥離し難い構造となっている。このため、ボンディングワイヤ３８が設けられている箇所では、ボンディングテープ４０のボンディング箇所の数を多くしても、絶縁樹脂層２２の放熱板からの剥離を十分に抑制することができる。 Since it is preferable to peel off at the loop portion of the bonding tape 40, it is preferable that there are few places where the bonding tape 40 is bonded to the lower heat sink 12. Therefore, in places where the bonding wire 38 is not provided, it is preferable that the bonding tape 40 is bonded only at both ends, as shown in FIG. Further, in the place where the bonding wire 38 is provided, as shown in FIG. 4, the bonding tape 40 is bonded to a portion other than both ends in order to lower the loop. However, as shown in FIG. 2, the width between the end faces of the semiconductor chip 14 and the lower heat sink 12 is a portion where the bonding wire 38 is provided (that is, the width W1), and the bonding wire 38 is not provided. Wider than the location (ie, width W2). Therefore, at the location where the bonding wire 38 is provided, the insulating resin layer 22 has a structure that is difficult to peel off from the lower heat radiating plate 12. Therefore, in the place where the bonding wire 38 is provided, even if the number of bonding parts of the bonding tape 40 is increased, the peeling of the insulating resin layer 22 from the heat sink can be sufficiently suppressed.

なお、上述した実施形態では、ボンディングテープ４０が下部放熱板１２の上面にボンディングされていた。しかしながら、ボンディングテープ４０が上部放熱板１８の下面にボンディングされていてもよい。 In the above-described embodiment, the bonding tape 40 is bonded to the upper surface of the lower heat sink 12. However, the bonding tape 40 may be bonded to the lower surface of the upper heat sink 18.

以上、実施形態について詳細に説明したが、これらは例示にすぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例をさまざまに変形、変更したものが含まれる。本明細書または図面に説明した技術要素は、単独あるいは各種の組み合わせによって技術有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの１つの目的を達成すること自体で技術有用性を持つものである。 Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. The technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Further, the techniques exemplified in the present specification or the drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

１０ ：半導体装置
１２ ：下部放熱板
１４ ：半導体チップ
１６ ：金属ブロック
１８ ：上部放熱板
２０ ：信号端子
２２ ：絶縁樹脂層
３０ ：はんだ層
３２ ：はんだ層
３４ ：はんだ層
３８ ：ボンディングワイヤ
４０ ：ボンディングテープ 10: Semiconductor device 12: Lower heat dissipation plate 14: Semiconductor chip 16: Metal block 18: Upper heat dissipation plate 20: Signal terminal 22: Insulation resin layer 30: Solder layer 32: Solder layer 34: Solder layer 38: Bonding wire 40: Bonding tape

Claims (1)

半導体装置であって、
第１表面を有する第１放熱板と、
前記第１表面に対向する第２表面を有する第２放熱板と、
前記第１表面の一部と前記第２表面の一部に接続されている半導体チップと、
前記第１表面にループ状にボンディングされており、前記半導体チップの外周縁に沿って伸びるボンディングテープと、
前記第１表面と前記第２表面に接しており、前記半導体チップと前記ボンディングテープを封止する絶縁樹脂層、
を有し、
前記ボンディングテープの前記絶縁樹脂層に対する密着強度が、前記第１放熱板及び前記第２放熱板の前記絶縁樹脂層に対する密着強度よりも低い、
半導体装置。 It ’s a semiconductor device,
A first heat sink with a first surface and
A second heat sink having a second surface facing the first surface,
A semiconductor chip connected to a part of the first surface and a part of the second surface,
A bonding tape bonded to the first surface in a loop shape and extending along the outer peripheral edge of the semiconductor chip.
An insulating resin layer that is in contact with the first surface and the second surface and seals the semiconductor chip and the bonding tape.
Have,
The adhesion strength of the bonding tape to the insulating resin layer is lower than the adhesion strength of the first heat sink and the second heat sink to the insulating resin layer.
Semiconductor device.
JP2018033471A 2018-02-27 2018-02-27 Semiconductor device Active JP7017093B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2018033471A JP7017093B2 (en) 2018-02-27 2018-02-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018033471A JP7017093B2 (en) 2018-02-27 2018-02-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2019149468A JP2019149468A (en) 2019-09-05
JP7017093B2 true JP7017093B2 (en) 2022-02-08

Family

ID=67850752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018033471A Active JP7017093B2 (en) 2018-02-27 2018-02-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP7017093B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068602A (en) 1999-06-25 2001-03-16 Oki Electric Ind Co Ltd Semiconductor device
JP2002110893A (en) 2000-10-04 2002-04-12 Denso Corp Semiconductor device
JP2003163314A (en) 2001-11-27 2003-06-06 Kyocera Corp Semiconductor device
JP2006120970A (en) 2004-10-25 2006-05-11 Toyota Motor Corp Semiconductor module and its manufacturing method
JP2009141053A (en) 2007-12-05 2009-06-25 Denso Corp Lead frame and manufacturing method of semiconductor device
US20100327421A1 (en) 2009-06-30 2010-12-30 Stmicroelectronics Asia Pacific Pte. Ltd. Ic package design with stress relief feature
JP2014139968A (en) 2013-01-21 2014-07-31 Toyota Motor Corp Semiconductor device and manufacturing method of the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0774291A (en) * 1993-09-03 1995-03-17 Hitachi Cable Ltd Heat sink material for semiconductor device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001068602A (en) 1999-06-25 2001-03-16 Oki Electric Ind Co Ltd Semiconductor device
JP2002110893A (en) 2000-10-04 2002-04-12 Denso Corp Semiconductor device
JP2003163314A (en) 2001-11-27 2003-06-06 Kyocera Corp Semiconductor device
JP2006120970A (en) 2004-10-25 2006-05-11 Toyota Motor Corp Semiconductor module and its manufacturing method
JP2009141053A (en) 2007-12-05 2009-06-25 Denso Corp Lead frame and manufacturing method of semiconductor device
US20100327421A1 (en) 2009-06-30 2010-12-30 Stmicroelectronics Asia Pacific Pte. Ltd. Ic package design with stress relief feature
JP2014139968A (en) 2013-01-21 2014-07-31 Toyota Motor Corp Semiconductor device and manufacturing method of the same

Also Published As

Publication number Publication date
JP2019149468A (en) 2019-09-05

Similar Documents

Publication Publication Date Title
CN111446217B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
KR100511728B1 (en) Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same
US6867484B2 (en) Semiconductor device
JP7441287B2 (en) semiconductor equipment
JP3329073B2 (en) Semiconductor device and manufacturing method thereof
US8089141B1 (en) Semiconductor package having leadframe with exposed anchor pads
JPS61241959A (en) Semiconductor module
JPS6324647A (en) Semiconductor package
KR102231769B1 (en) Semiconductor package having exposed heat sink for high thermal conductivity and manufacturing method thereof
CN104412382A (en) Semiconductor device
JP7006812B2 (en) Semiconductor device
JP7247574B2 (en) semiconductor equipment
JP2007012831A (en) Power semiconductor device
JP2010283053A (en) Semiconductor device and method for manufacturing the same
JP4967701B2 (en) Power semiconductor device
JP2003163314A (en) Semiconductor device
JP7195208B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP2017123360A (en) Semiconductor module
JP7017093B2 (en) Semiconductor device
JP2017135144A (en) Semiconductor module
US20100224982A1 (en) Lead and lead frame for power package
US20100052190A1 (en) Semiconductor device
JP2008211168A (en) Semiconductor device and semiconductor module
JPS6050354B2 (en) Resin-encapsulated semiconductor device
JP7419781B2 (en) semiconductor module

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20200401

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20210212

TRDD Decision of grant or rejection written
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20211222

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20211228

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20220110