WO2005006432A2 - Electronic component and method for production thereof - Google Patents

Electronic component and method for production thereof Download PDF

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Publication number
WO2005006432A2
WO2005006432A2 PCT/EP2004/006500 EP2004006500W WO2005006432A2 WO 2005006432 A2 WO2005006432 A2 WO 2005006432A2 EP 2004006500 W EP2004006500 W EP 2004006500W WO 2005006432 A2 WO2005006432 A2 WO 2005006432A2
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WO
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Patent type
Prior art keywords
carrier substrate
ts
layer
cover plate
formed
Prior art date
Application number
PCT/EP2004/006500
Other languages
German (de)
French (fr)
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WO2005006432A3 (en )
Inventor
Christian Diekmann
Original Assignee
Epcos Ag
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Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/007Interconnections between the MEMS and external electrical signals
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • H03H9/1007Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/105Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the BAW device
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02Details
    • H03H9/05Holders; Supports
    • H03H9/10Mounting in enclosures
    • H03H9/1064Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1092Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/01Packaging MEMS
    • B81C2203/0118Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to the formation of vertical electrical through contacts in a support substrate, on the surface of which component structures are fixed, whereby the component structures are associated with contact surfaces, arranged over the through contacts. The component structures and the contact surfaces are arranged in cavities, formed by the direct wafer bonding of the carrier substrate with a cover sheet comprising a corresponding recess.

Description

description

Electronic device and method for producing

The invention relates to an electronic component which has arranged on the upper side of a carrier substrate sensitive component structures, and to processes for its preparation.

Such sensitive component structures such can. B. be electro-acoustic transducer or thin-film resonators of a (z. B. guaranteed by a respective housing) protection against environmental influences require.

It is possible to place the supporting substrate having formed on its top side component structures in a recess of a housing and seal off this recess from above. The electrical connection of the component structures provided on the underside of the housing pads of the component takes place, for. Example, by bonding wires and vertical electrical connections (vias) in the housing.

An advantageous Häusungstechnik (Wafer Level Package) is the support substrate with 'a cover plate z. connecting, by a wafer bonding method, whereby cavities are provided in the cover plate, which together with the top side of the carrier substrate cavities in which sensitive component structures are arranged. The leading to the outside vertical electrical connections are formed in advance in the cover plate, see, for example. For example, the document EP 1071126 A2. Contact surfaces of the carrier substrate and pads of the top plate are connected by a soldered together electrically and therefore must be precisely aligned (What 'high expenditure means), otherwise electrical properties of the device may be impaired. In the document EP 1070677 A2 an alternative solution for contacting the component structures is proposed, wherein the provided on the carrier substrate can be exposed therethrough to the component structures electrically connected to the contact surfaces after bonding the carrier substrate to the cover plate by the cover plate. These contact surfaces can then z. B. can be contacted via bonding wires. The disadvantage of this solution is that the contact surfaces are not easily accessible.

Object of the present invention is to provide an electronic device of the type mentioned, which is carried out in wafer level package technology and simple structure, and a method for its preparation.

The object of the invention is achieved by a device according to claim 1 and by a method according to claim 100th

The invention provides an electronic component, which is a

A carrier substrate, on the upper side of electro-acoustic, electromechanical and / or further to be protected active component structures are formed that are electrically and mechanically fixedly connected to the carrier substrate. On the underside of the carrier substrate a first metallization level and on its upper side a second metallization is provided. In the first metallization pads are formed, which are provided as external contacts of the component. In the second metallization contact surfaces are formed which are electrically connected to the device structures.

On the carrier substrate a cap (preferably a cover plate) is arranged, which has a cavity for the carrier substrate back and together with the carrier substrate (TS) on all sides forming a tight enclosed cavity into which the component structures are arranged. The chosen as a cover plate cap can be mechanically connected to the carrier substrate by a direct wafer bonding methods, for example by adhesive bonding, cold welding, soldering or anodic wafer bonding.

which connect the contact surfaces of the second metal with the terminal surfaces of the first electrically conductive metallization formed, - According to the invention the carrier substrate vertical electrically conductive connections - vias.

The invention is distinguished over the prior art by the fact that disposed to be protected sensitive component structures on the same substrate in which are formed the vertical electrical connections to the external contacts, whereby the most precise alignment of the cover plate on the support substrate is unnecessary. In this case also the soldering process, which is to make an electrical connection between the initially arranged in the cover plate vias and formed on the surface of the carrier substrate component structures is omitted.

The device structures are for. B. when working with thin film bulk acoustic resonators or working with surface acoustic waves or boundary waves transducers and reflectors formed. The resonators or transducers are electrically connected to each other and together form preferably a filter circuit.

The component structures can realize a MEMS element (MEMS = microelectromechanical system) beyond. It is also possible that the component structures at least one active (semiconductor) include element such. For example, a transistor, or a built-up of active elements

Circuit which z. B. realized an oscillator, an amplifier or a diode switch.

The cover plate is preferably made of silicon, glass or quartz. The cover plate has at least a dielectric layer. For electrical shielding also may be in the cap - may be provided an electrically conductive layer - preferably on the side remote from the carrier substrate side of the cap.

The carrier substrate may comprise one or more dielectric and / or semiconductor layers. In one at least one semiconductor layer having the carrier substrate, the vias are isolated from the base substrate by an electrically insulating layer.

The carrier substrate and the cover plate may be present in each case as wafers in the manufacture of the device.

In a development of the invention, at least two semiconductor layers are provided in the carrier substrate, between which an insulating layer is arranged.

In an advantageous variant of the invention a bonding layer is provided between the support substrate and the cover plate, for. As an adhesive layer or Si0 2 layer. The connecting layer preferably as Si0 2 layer may be performed z. B. a large area covering the upper surface of the support substrate having disposed thereon the component structures and the component structures tightly enclose and thereby take over the role of a trimming layer for adjusting the resonance frequency of individual resonators.

In another variant of the invention, the bonding layer may be applied to the wearer facing towards the substrate surface of the cover plate. The

Compound layer is preferably hermetically sealed. In an advantageous variant, the link layer is extensively applied to the excavations side having the cover plate. but it is also possible to apply the bonding layer only on the areas of the corresponding surface of the cover plate, which are directly connected to the top of the carrier substrate.

Among soldering two substrates, a compound is understood in the present invention, brought about by the melting of a arranged between the two substrates bonding layer and then solidifying the temperature preferably does not exceed 400 ° C.

Under cold welding is understood to mean a connection of two substrates, wherein the elevated pressure (without any thermal treatment) at the interface of the two substrates

diffused material of a substrate in the material of the other substrate.

The pads can be used in SMD technology (SMD = Surface Mounted Device) with a base plate, z. For example, the printed circuit board of a terminal to be connected.

A vertical electrical connection between a contact surface and a pad, by a plurality of, in each case through the carrier substrate underpassing

Vias (Kontaktlδcher) be realized.

In a further development of the invention, a piezoelectric layer disposed between the carrier substrate and the second metallization plane, wherein operating in the second metallization including surface acoustic wave device structures are formed.

Instead of the piezoelectric layer, or in addition to the piezoelectric layer further functional layers can be disposed between the support substrate and the second metallization plane, which together z. B. forming a functional layer system. In this case, the via holes are passed through the carrier substrate and the functional layer system therethrough.

An inventive method for preparing the

Device, for example, comprises the steps of:

The device structures are placed on top of a carrier substrate and electrically connected to the contact surfaces. There is a cover plate with

provided cavities on one of its major surfaces and connected to the carrier substrate so that the component structures between the carrier substrate and the cover plate are enclosed in a cavity formed by the cavities. In the supporting substrate

Vias generated which connect the contact areas through the carrier substrate through electrically connected to formed on the underside of the carrier substrate pads.

The carrier substrate and the cover plate are joined in a direct wafer bonding methods such. B. joined by cold welding, anodic bonding method or Grid bonding.

Preferably, several devices are formed in a large area wafer and then separated, with the large-area wafer is formed through the carrier substrate to the vias, which is connected to the cover plate.

During the creation of the vias through vertical openings are made in the carrier substrate first, which are subsequently metallised or filled with electrically conductive material.

In a variant of the invention, the vertical openings after the bonding of the support substrate and the cover plate z. B. forth produced by etching (preferably anisotropic etching) through the carrier substrate to pass from the underside of the carrier substrate in direction of the opposite contact surface. The respective contact surface serves as an etch stop. The openings thus formed are then metallized by the underside of the carrier substrate side, wherein preferably also the bonding pads of the component are generated in the same process step. but it is also possible to fill the vertical openings with electrically conductive material and (seen from below) also apply a metal layer in which so corresponding pads are formed directly under the vias thus formed.

It is possible to create the vias in the carrier substrate and prior to joining the carrier substrate and the cover plate. The vias may be formed on the carrier substrate before or after the arrangement of the component structures.

In a variant of the invention are preferably produced prior to placement of the component structures of the top of the carrier substrate side blind holes, which are subsequently metallised or filled with electrically conductive material, wherein the contact surfaces are formed on the filled Sacklδchern or in the vicinity of the metallized blind vias. Also, the exposed surface of a metal-filled blind hole may be provided as contact surface. In the preferred embodiment of the invention, the contact surfaces are in a

formed metal layer, which is applied on top of the carrier substrate after the plating or filling of blind holes.

To expose the metallization or metal filling

Blind holes on the underside of the carrier substrate, the carrier substrate is thinned from the lower side. The plated-through holes, which constitute vertical electrical connections between the contact areas on the top side of the carrier substrate and the pads on the underside of the carrier substrate are formed.

The thinning of the carrier substrate may occur before or after joining the carrier substrate and the cover plate. The thinning of the carrier substrate after the bonding with the cover plate has the advantage that the wafer, which is formed from the carrier substrate and the top plate due to a higher thickness in view of the mechanical processing such as thinning is more stable than the support substrate alone. The device can now be thinned to the predetermined (low) component height.

In a further variant of the inventive method intended for later plated-through holes in the carrier substrate openings or blind holes are initially lined with an electrically insulating layer and subsequently metallised or filled with electrically conductive material. The lining of the electrically insulating layer may be preferably made of thermal oxide z. B. generated by rapid thermal processing. This variant of the invention is particularly advantageous - would connect to a support substrate having at least one semiconductor layer having different vias otherwise electrically conducting - in terms of electrical insulation of the vias from each other.

In an advantageous variant of the invention may be on the

Upper surface of the support substrate or a dielectric layer provided on the side facing the carrier substrate side of the cover plate, which ensures a good adhesion and a hermetically sealed connection between the adjoining regions of the base substrate and the cover plate. An electro-acoustic transducer embodied as Bauelement- structure such can. B. be formed in the following process steps:

On the upper side of the carrier substrate, a piezoelectric layer is applied. The piezoelectric layer may be on the carrier substrate such. B. are grown epitaxially. passing through the piezoelectric layer through the blind holes in the laminate of the support substrate and the piezoelectric layer preferably after forming the metallized or filled, - - on the piezoelectric layer is placed a patterned metal layer in which the contact surfaces and at least a part of the component structures are formed. The vias are formed in this variant of the invention by the support substrate and the piezoelectric layer.

A designed as a thin film resonator element structure such can. B. be formed in the following process steps:

At least a portion of the component structures on the top side of the carrier substrate is formed as a layer system whose layers applied over one another and are structured to electrically interconnected thin-film resonators. In this case, initially, at least a bottom electrode layer, then a piezoelectric layer and at least an upper electrode layer coated thereon, wherein each electrode is formed in the upper and the lower electrode layer.

In the construction of the layer system on the carrier substrate are in an advantageous variant of the invention, first layers for producing an acoustic mirror, and only then the lower electrode layer and subsequent

Layers of the layer system applied. The thin-film resonators may be arranged over an opening provided in the carrier substrate recess.

Before applying the respective electrode layer by the previously applied layers of the layer system through formed openings over some of the contact surfaces and exposed in this manner the contact surfaces from above, wherein the respective electrode layer is applied in such a way and structured such that the openings of the layer system in edge-conductive with electrically material to be lined and thereby an electrical connection between the contact surfaces and the electrodes of the respective (in particular, upper) electrode layer is prepared.

The invention is based on Ausfuhrungsbei- play and explained in detail the associated figures. The figures show by way of schematic and not to scale representations of various embodiments of the invention. Identical or identically acting parts are designated by like reference numerals.

Show it

Figure 1 schematically illustrates a known method for forming vias in a substrate.

2 schematically shows steps of an inventive method for manufacturing a device with thin-film resonators.

3a shows the bottom view of the large surface area formed cover plate which is to be connected to a carrier substrate.

3b shows the top view on the large surface area formed carrier substrate, which is connected to the cover plate in Figure 3a schematically illustrated. Figure 4 schematically illustrates steps of a method according to the invention for the preparation of a working surface acoustic wave device.

5 shows a variant of the invention in which the vias are produced in the supporting substrate before bonding the carrier substrate with the cover plate.

6 shows an advantageous variant in which a compound layer is applied on top of the carrier substrate with device structures, serving in connecting the carrier substrate to the cover plate as an adhesion layer of the invention.

Figure 7 is a further development in which the connecting layer is applied to the underside of the cover plate of the invention.

Figure 8 detail of an inventive device with an advantageous embodiment of the vias.

1 shows a known method for producing vias in a substrate SU. The substrate SU, a blind hole DE is generated for example by etching in method step a). The blind hole is preferably lined in process step b) (particularly in a semiconducting substrate SU) with an electrically insulating layer. In the next procedural step c) is applied to the top of the substrate SU an electrically conductive material FM, which also fills the blind holes DE. In process step d) the electrically conductive material FM is removed from the top of the substrate SU, wherein the electrically conductive material FM remains in the blind holes. In process step e) directly over the filled sack hole has a contact surface KF2 is formed in a metallization ME2. The substrate SU is thinned from the lower side, for example, by thinning the wafers by grinding and then chemical mechanical polishing until the metallization of the blind hole is exposed. In process step f) a connection surface is formed in a metallization ME1 KF1 directly below the thus formed via DK.

2 shows the first variant of the inventive method is explained. The first, not shown process steps correspond to the process steps a) to d) of the method explained in Figure 1 already. In the next step (see step a) in Figure 2) one after the other, the layers of an acoustic mirror AK be applied on top of the carrier substrate TS. In process step b) the layers of the acoustic mirror AK, for example, by etching structured such that at least portions of the contact surfaces KF2 are exposed. Also, for joining provided to the cover plate portions of the upper surface of the support substrate are preferably exposed.

In process step c) a lower electrode layer UE is first applied or textured, so that an electrode is formed over the acoustic mirror AK, respectively, which is electrically connected with the contact surface KF2. Over the lower electrode, a piezoelectric layer structured PS is applied. On the piezoelectric layer PS an upper electrode layer OE is applied, in which an upper electrode is formed over the lower electrode, which is electrically connected to a not shown in this figure contact surface.

The TS to the carrier substrate above the other applied layers forming the layers of a layer system SS. The lower electrode, the piezoelectric layer and the upper electrode forming a thin-film resonator RE. The resonator RE and the acoustic mirror AK together form a device structure BS.

The top of the support substrate having disposed thereon thin-film resonators is in a variant of the invention, preferably a large area with a trimming layer TR z. B. coated silicon oxide, wherein the trim layer surrounds the component structures BS and a tight seal with the carrier substrate TS. The trim layer TR serves for example for frequency tuning of the device and also as a

Link layer or adhesive layer when joining the carrier substrate TS with the cover plate CAP.

In the preferred embodiment of the invention, the carrier substrate TS is first connected to the cover plate and then thinned from below to form vias.

The cover plate CAP has a cavity on AH, which is turned towards the supporting substrate and TS in connecting the carrier substrate to the cover plate, the component structures

receives BS (step d) of Figure 2) and forms a cavity HR this component structures.

In another variant of the invention, the carrier substrate TS is thinned from its underside before being joined to the cover plate. The Sacklδcher DE DK into the corresponding plated-through holes to be converted.

in process step d) on the underside of

A carrier substrate TS metallization ME1 applied, are formed in the provided as external contacts of the component pads KF1. The pads KF1 are disposed directly under the vias DK. In a variant of the invention, the exposed bottom of a via itself can be used as a pad.

Figure 3a shows in a schematic bottom view of a large-area cover plate CAP, in which a plurality of cavities AH are formed for example by pressing or etching, and are provided for a later recording of the component structures BS.

The cavities are preferably produced by AH Phototechnik in a wet etching process.

3b shows a schematic plan view is shown on a wafer, which is formed by connecting the large-area substrate formed carrier TS and the large surface area formed cover plate CAP. The non visible from the outside, the component structures BS receiving cavities HR are indicated by dashed lines. The other lines TL give the (imaginary) lines of separation along which the devices produced on the carrier substrate in parallel are separated.

Figure 4 illustrates an inventive method for manufacturing a working surface acoustic wave device. In process step a), a piezoelectric layer PS is applied to the carrier substrate TS. In process step b), the blind holes are produced in the DE composite of the carrier substrate TS and the piezoelectric layer PS, wherein the respective blind hole DE through the piezoelectric layer PS goes all the way through.

In process step c) the blind hole DE is preferably lined with an electrically and / or thermally insulating layer IS and filled with an electrically conductive material FM. The electrically conductive material may be, for FM. B. be thermally deposited tungsten or an electrically conductive paste with doctor blade.

In all variants of the invention, it is possible to metallize only the surface of tangible hole DE instead of the full replenishment of the blind hole DE. It is possible to form the electrically connected to this metallization contact surfaces in the same process step.

In method step d) a metallization is applied to the piezoelectric layer PS provided as a second metallization ME2.

In process step e) this metallization is structured such that the contact surfaces KF2 be formed over the blind holes DE, the transducers WA) are electrically connected (with the formed also in the second metallization ME2 component structures here z. B.. The construction of the device according to the invention after the process step e) is (in schematic cross-sectional top) and a schematic plan view from above (directly below) is shown.

In process step f) a tie layer VS is applied, for example, to the support substrate in the TS with the cover plate portions to be joined. It is also possible to apply the connection layer VS alternatively on the underside of the cover plate CAP, at least in the areas on the underside of the cover plate CAP that will later be connected to the carrier substrate TS. The connecting layer VS serves to hermetically seal the cavity

MR. In the process steps f) and g) (before or after bonding the carrier substrate to the cover plate), the vias DK and the pads KF1 z. B. produced in a process according to FIG. 1

In the presented in Figure 4 variant of the invention the thinning of the base substrate is made only after the connection to the cover plate. The subsequent thinning of the base substrate has been compared with the variant of the invention, are generated in the place blind holes identical through holes, the advantage that the carrier substrate having a required for processing (large) thick at the beginning, later reduced to reduce the overall height of the component can be.

It is possible, as indicated in Figures 4 and 5, the connecting layer VS to the piezoelectric layer PS preferably applied in the fields of which are bonded directly to the cover plate CAP. In the figure, 5 is also indicated, that the vias are formed in the carrier substrate DK TS before bonding the carrier substrate to the cover plate.

In the embodiment shown in Figure 6 variant of the invention the carrier substrate TS is of semiconductive material, such. Example, of silicon. For electrical insulation of the Bauelementstruk- BS structures (or contact surfaces KF2) from each other is arranged an electrically and preferably also thermally insulating layer ISL between the second metallization and the carrier substrate.

Instead of the insulating layer ISL can also another functional layer or a functional layer system may be provided (in conjunction with a carrier substrate made of a dielectric or semiconducting material) z. B. plate serves as a tie layer between the carrier substrate and of the cover. The functional layers may also be to

serve frequency tuning of the device, or to compensate for different thermal expansion coefficients of the support substrate and the lower layers of the structures Bauelement- BS.

7 shows a further variant of the invention in which the connecting layer VS is applied to the large area turned towards the supporting substrate side of the cover plate TS CAP.

In Figure 8, a component of the invention is fragmentary presented in which the via DK, which connects the contact surface KF2 and the pad KF1 to each other, arranged in several adjacent, vertical electrically conductive connections is formed.

Although in the embodiments, only a limited number of possible developments of the invention has been described, the invention is not limited to these. It is possible to electro-acoustically active structures such. B. produce transducers and reflectors in any number and shape so as to change the characteristics of the device in a desired manner. A component of the invention is not limited to the above materials, the number of elements shown or to specific frequency ranges.

Claims

claims
1. An electronic component comprising a carrier substrate (TS), arranged with one on the carrier substrate (TS) and firmly connected thereto, the cover plate (CAP), which together with the carrier substrate (TS) has a cavity (HR), wherein on the underside of carrier substrate (TS), a first metallization (Mel) and a second metallization on its upper side (ME2) are provided, wherein the first metallization level (MEL) comprises pads (KF1), wherein in the second metallization plane (ME2) contact surfaces (KF2) are formed wherein on the top side of the carrier substrate (TS) electro-acoustic, electro-mechanical or active device structures (BS) are arranged, which are fixedly connected to the carrier substrate, the component structures (BS) in the cavity (HR) and electrically connected to the contact surfaces (KF2) are connected, wherein the carrier substrate (TS) via holes (DK) are constructed which the contact surfaces (KF2) with de n pads (KF1) to connect electrically conductive.
2. The component according to claim 1, wherein the cover plate (CAP) includes at least one dielectric layer.
The device of claim 1 or 2, wherein the carrier substrate (TS) has at least two semiconductor layers, between which an insulating layer is provided.
realize component according to one of claims 1 to 3, in which the component structures (BS) at least one working with bulk acoustic waves resonator (RE).
5. The component according to claim 4, wherein between the resonator (RE) and the carrier substrate (TS) an acoustic mirror (AK) is arranged.
6. The component according to any one of claims 1 to 5, in which between the second metallization (MS2) and the carrier substrate (TS), a piezoelectric layer (PS) is arranged in which the component structures (BS) in the second metallization (MS2) formed and are thereby at least realize an operating with acoustic surface or boundary wave converter.
7. The component according to any one of claims 1 to 6, in which between the second metallization plane (ME2) and the carrier substrate (TS), an electrically insulating layer (ISL) is arranged.
8. The component according to any one of claims 1 to 7, wherein the outer side of the cover plate (CAP) metallized.
9. The component according to one of claims 1 to 8, wherein the cover plate (CAP) at least one layer of glass or quartz comprises.
10.A process for manufacturing an electronic component comprising the steps of: placing the component structures (BS) on the top side of a carrier substrate (TS), which has on its upper side contact surfaces (KF2), and electrically connecting the component structures (BS) to the contact surfaces (KF2 ), - providing a cover plate (CAP) with cavities (AH) on one of its main surfaces,
- connecting the carrier substrate (TS) and the cover plate (CAP) so that the component structures (BS) between the carrier substrate (TS) and the cover plate (CAP) in a through the cavities (AH) formed cavity (HR) are included, generating vias (DK) in the carrier substrate (TS), - generating pads (KF1) on the underside of the carrier substrate (TS).
11. The method according to claim 10, wherein the carrier substrate (TS) is formed with at least one semiconductor layer, wherein for generating the vias (DK) generates openings in the carrier substrate, and initially with an electrically insulating layer (IS) lined and subsequently metallized or with electrically conductive material to be filled.
12.A method according to claim 10, wherein before bonding the carrier substrate (.TS) and the cover plate (CAP), before or after the arrangement of the component structures (BS) on the carrier substrate (TS) first blind holes (DE) in the upper surface of the support substrate are formed (TS) which are subsequently metallised or filled with electrically conductive material, over the filled blind holes (DE) or in the vicinity of the metallized blind holes (DE), the contact surfaces (KF2) are formed, in which before or after bonding of the carrier substrate (TS) and the cover plate (CAP), the carrier substrate (TS) from the lower side is thinned until there the filler material or the metallization of the blind holes (DE) is exposed, and then the plated-through holes (DK) is formed of the carrier substrate (TS) are - providing pads (KFl) on the underside of the carrier substrate (TS).
be lined 13. The method of claim 12, wherein the carrier substrate (TS) is formed with at least one semiconductor layer, wherein prior to filling in the blind holes (DE) with electrically conductive material, these blind holes (DE) with an electrically insulating layer (IS) ,
14. A method according to any one of claims 10 to 13, wherein the carrier substrate (TS) and the cover plate (CAP) by means of cold welding, anodic bonding method, bonding or soldering grid are connected.
15. The method of claim 14, wherein on the top side of the carrier substrate (TS) or on to the carrier substrate (TS) side facing the cover plate (CAP) a dielectric layer (VS) is provided, which connects between the adjacent regions of the carrier substrate (TS) and the cover plate (CAP) ensured.
wherein then the piezoelectric layer (PS) a structured metal layer is located 16. The method according to any one of claims 10 to 14, in which first a piezoelectric layer (PS) on the top side of the carrier substrate (TS) is placed, which the contact surfaces (KF2) and at least a portion of the component structures (BS) comprises, in which the plated-through holes (DK) through the carrier substrate (TS) and the piezoelectric layer (PS) therethrough are formed.
17. The method according to any one of claims 10 to 16, wherein at least a part of the component structures (BS) on the top side of the carrier substrate (TS) constructed as a layer system whose layers applied over one another and electrically interconnected thin-film resonators (RE) structured are, initially, at least a lower electrode layer (UE), then a piezoelectric layer (PS) and on it, at least one upper electrode layer is applied (OE), and wherein electrodes are formed in the upper and the lower electrode layer (OE, UE), respectively.
18.A process according to claim 17, wherein on the carrier substrate in the construction of the layer system (TS), first layers to produce an acoustic mirror (AK) and then the lower electrode layer (UE) and subsequent layers of the layer system are applied.
generated 19.A method according to claim 18, wherein prior to the application of the respective electrode layer (UE, OE) through the previously applied layers of the layer system openings, and in the contact surfaces (KF2) are exposed, wherein the respective electrode layer (UE, OE is) is applied and structured in such a way that the openings of the layer system are in edge-lined with electrically conductive material and thus an electrical connection between the contact surfaces (KF2), and the electrodes of the respective electrode layer (UE, OE) is produced.
20.A process according to any one of claims 17 to 19, wherein on the surface of the component structures (BS) and of the carrier substrate (TS), a thin layer is deposited which serves as a trim layer and the connecting layer (VS).
21. The method according to any one of claims 10 to 20, wherein a plurality of devices formed in or on a large area, as the carrier substrate (TS) serving wafer, with a large-area cover plate (CAP) and are then separated.
PCT/EP2004/006500 2003-07-10 2004-06-16 Electronic component and method for production thereof WO2005006432A3 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10331322.2 2003-07-10
DE2003131322 DE10331322A1 (en) 2003-07-10 2003-07-10 Electronic device and method for producing

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