WO2005006432A2 - Composant electronique et procede de fabrication - Google Patents

Composant electronique et procede de fabrication Download PDF

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Publication number
WO2005006432A2
WO2005006432A2 PCT/EP2004/006500 EP2004006500W WO2005006432A2 WO 2005006432 A2 WO2005006432 A2 WO 2005006432A2 EP 2004006500 W EP2004006500 W EP 2004006500W WO 2005006432 A2 WO2005006432 A2 WO 2005006432A2
Authority
WO
WIPO (PCT)
Prior art keywords
carrier substrate
layer
cover plate
component
cap
Prior art date
Application number
PCT/EP2004/006500
Other languages
German (de)
English (en)
Other versions
WO2005006432A3 (fr
Inventor
Christian Diekmann
Original Assignee
Epcos Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epcos Ag filed Critical Epcos Ag
Publication of WO2005006432A2 publication Critical patent/WO2005006432A2/fr
Publication of WO2005006432A3 publication Critical patent/WO2005006432A3/fr

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H03H9/105—Mounting in enclosures for bulk acoustic wave [BAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the BAW device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H03H9/1092—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/01—Packaging MEMS
    • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to an electronic component which has sensitive component structures arranged on the upper side of a carrier substrate, and to methods for its production.
  • Such sensitive component structures can e.g. B. be electroacoustic transducers or thin-film resonators, which require protection against environmental influences (eg ensured by a corresponding housing).
  • An advantageous housing technology (wafer level package) consists in that the carrier substrate with ' a cover plate z. B. by a wafer bonding process, wherein in the cover plate cavities are provided which form cavities together with the top of the carrier substrate, in which sensitive component structures are arranged.
  • the vertical electrical connections leading to the outside are already formed beforehand in the cover plate, see, for. B. EP 1071126 A2.
  • Contact surfaces of the carrier substrate and connection surfaces of the cover plate are electrically connected to one another by a solder connection and must therefore be aligned precisely with one another (which means a great deal of effort), since otherwise the electrical properties of the component can be impaired.
  • the object of the present invention is to provide an electronic component of the type mentioned at the outset, which is implemented using wafer level package technology and is of simple construction, and a method for its production.
  • the object of the invention is achieved by a component according to claim 1 and by a method according to claim 100.
  • the invention provides an electronic component that a
  • a first metallization level is provided on the underside of the carrier substrate and a second metallization level is provided on its top side.
  • connection surfaces are formed which are provided as external contacts of the component.
  • Contact surfaces are formed in the second metallization level, which are electrically connected to the component structures.
  • a cap (preferably a cover plate) is arranged on the carrier substrate, which has a cavity toward the carrier substrate and, together with the carrier substrate (TS), forms a cavity which is tightly enclosed on all sides and in which the component structures are arranged.
  • the cover plate selected can be mechanically connected to the carrier substrate by a direct wafer bonding method, for example by an adhesive connection, cold welding, soldering or anodic wafer bonding.
  • vertical electrically conductive connections — vias — are formed in the carrier substrate, which electrically conductively connect the contact areas of the second metallization level to the connection areas of the first metallization level.
  • the invention distinguishes itself from the prior art in that the sensitive component structures to be protected are arranged on the same substrate in which the vertical electrical connections to the external contacts are also formed, as a result of which the particularly precise alignment of the cover plate on the carrier substrate is unnecessary.
  • the soldering process which is intended to establish an electrical connection between the plated-through holes originally arranged in the cover plate and component structures formed on the surface of the carrier substrate, is also eliminated.
  • the component structures are e.g. B. designed as working with bulk acoustic waves resonators or working with surface acoustic waves or boundary waves transducers and reflectors.
  • the resonators or transducers are electrically connected to one another and preferably together form a filter circuit.
  • Circuit the z. B. an oscillator, an amplifier or realized a diode switch.
  • the cover plate is preferably made of silicon oxide, glass or quartz.
  • the cover plate has at least one dielectric layer.
  • an electrically conductive layer can also be provided in the cap, preferably on the side of the cap facing away from the carrier substrate.
  • the carrier substrate can have one or more dielectric and / or semiconductor layers.
  • the plated-through holes are insulated from the carrier substrate by an electrically insulating layer.
  • the carrier substrate and the cover plate can each be present as wafers during the production of the component.
  • At least two semiconductor layers are provided in the carrier substrate, between which an insulating layer is arranged.
  • connection layer is provided between the carrier substrate and the cover plate, for. B. an adhesive layer or Si0 2 layer.
  • the connection layer which is preferably embodied as an SiO 2 layer, can, for. B. extensively cover the top of the carrier substrate with component structures arranged thereon and tightly enclose the component structures and thereby take on the role of a trimming layer for adjusting the resonance frequency of individual resonators.
  • the connecting layer can be applied to the surface of the cover plate facing the carrier substrate.
  • connection layer is preferably hermetically sealed.
  • the connection layer is in an advantageous variant applied extensively to the side of the cover plate with the hollows. However, it is also possible to apply the connection layer only to the regions of the corresponding surface of the cover plate that are connected directly to the top of the carrier substrate.
  • soldering of two substrates is understood to mean a connection which is brought about by melting a connection layer arranged between the two substrates and then solidifying, the temperature preferably not exceeding 400 ° C.
  • Cold welding is a connection of two substrates, in which under increased pressure (without thermal influence) at the interface of the two substrates
  • Material of a substrate diffuses into the material of the other substrate.
  • SMD Surface Mounted Device
  • a vertical electrical connection between a contact surface and a connection surface can be made through a plurality, each of which leads through the carrier substrate
  • Vias contact holes
  • a piezoelectric layer is arranged between the carrier substrate and the second metallization level, component structures working with surface waves being formed in the second metallization level.
  • further functional layers can be arranged between the carrier substrate and the second metallization level.
  • component includes the following steps:
  • the component structures are arranged on the upper side of a carrier substrate and electrically connected to the contact areas. There will be a cover plate with
  • Cavities are provided on one of their main surfaces and connected to the carrier substrate in such a way that the component structures between the carrier substrate and the cover plate are enclosed in a cavity formed by the cavities. Be in the carrier substrate
  • Vias are produced which electrically connect the contact areas through the carrier substrate to connection areas formed on the underside of the carrier substrate.
  • the carrier substrate and the cover plate are joined together in a direct wafer bonding process, e.g. B. connected by cold welding, anodic bonding or grid bonding.
  • a direct wafer bonding process e.g. B. connected by cold welding, anodic bonding or grid bonding.
  • a plurality of components are preferably formed in a large-area wafer and then separated, the large-area wafer being formed by the carrier substrate with the plated-through holes which is connected to the cover plate.
  • the vertical openings are only after the connection of the carrier substrate and the Cover plate z. B. by etching (preferably anisotropic etching) through the carrier substrate from the bottom of the carrier substrate in the direction of the opposite contact surface.
  • the respective contact surface serves as an etch stop.
  • the openings formed in this way are then metallized from the underside of the carrier substrate, the connection surfaces of the component preferably also being produced in the same method step.
  • the plated-through holes can be produced before or after the arrangement of component structures on the carrier substrate.
  • blind holes are produced from the top of the carrier substrate, which are subsequently metallized or filled with electrically conductive material, the contact surfaces being formed over the filled blind holes or in the vicinity of the metallized blind holes.
  • the exposed surface of a blind hole filled with metal can also be provided as a contact surface.
  • the contact surfaces are in one
  • Metal layer formed which is applied to the top of the carrier substrate after metallizing or filling blind holes.
  • the carrier substrate is thinned from the bottom. there the vias are formed, which represent vertical electrical connections between the contact areas on the upper side of the carrier substrate and the connection areas on the underside of the carrier substrate.
  • the thinning of the carrier substrate can take place before or after the connection of the carrier substrate and the cover plate.
  • the thinning of the carrier substrate only after the connection to the cover plate has the advantage that the wafer, which is formed from the carrier substrate and the cover plate, is more stable than the carrier substrate alone due to a higher thickness in terms of mechanical processing, like thinning.
  • the component can now be thinned to the specified (low) component height.
  • the openings or blind holes provided for later plated-through holes in the carrier substrate are first lined with an electrically insulating layer and then metallized or filled with electrically conductive material.
  • the lining of the electrically insulating layer can preferably be made of thermal oxide such. B. generated by rapid thermal processing.
  • This variant of the invention is particularly advantageous - with regard to the electrical insulation of the vias from one another - in the case of a carrier substrate with at least one semiconductor layer which would otherwise connect various vias in an electrically conductive manner.
  • a dielectric layer can be provided on the upper side of the carrier substrate or on the side of the cover plate facing the carrier substrate, which dielectric layer ensures good adhesion or a hermetically sealed connection between the adjoining regions of the carrier substrate and the cover plate.
  • a component structure designed as an electroacoustic transducer can, for. B. are formed in the following process steps:
  • a piezoelectric layer is applied to the top of the carrier substrate.
  • the piezoelectric layer can on the carrier substrate z.
  • a structured metal layer, in which the contact surfaces and at least some of the component structures are formed, is arranged on the piezoelectric layer, preferably after the metallized or filled blind holes in the composite of the carrier substrate and the piezoelectric layer have been formed, which pass through the piezoelectric layer.
  • the vias are formed through the carrier substrate and the piezoelectric layer.
  • a component structure designed as a thin-film resonator can e.g. B. are formed in the following process steps:
  • At least some of the component structures on the upper side of the carrier substrate are designed as a layer system, the layers of which are applied one above the other and structured to form electrically interconnected thin-film resonators. First, at least one lower electrode layer, then a piezoelectric layer and then at least one upper electrode layer are applied, electrodes being formed in the upper and lower electrode layers.
  • layers are first used to produce an acoustic mirror and only then the lower electrode layer and the subsequent one
  • the thin film Resonators can also be arranged over a recess provided in the carrier substrate.
  • openings are formed through the previously applied layers of the layer system and over some of the contact areas, thus exposing the contact areas from above, the respective electrode layer being applied and structured in such a way that the openings of the layer system cover the edges with electrically conductive Lined material and thereby an electrical connection between the contact surfaces and the electrodes of the respective (in particular upper) electrode layer is made.
  • Figure 1 schematically shows a known method for producing vias in a substrate.
  • Figure 2 schematically process steps of a method according to the invention for producing a component with thin-film resonators.
  • Figure 3a shows the bottom view of the large-area cover plate, which is to be connected to a support substrate.
  • FIG. 3b shows the view from above of the large-area carrier substrate which is connected to the cover plate shown schematically in FIG. 3a.
  • FIG. 4 schematically, process steps of a method according to the invention for producing a component working with surface acoustic waves.
  • Figure 5 shows a variant of the invention, in which the plated-through holes in the carrier substrate are produced before the carrier substrate is connected to the cover plate.
  • Figure 6 shows an advantageous variant of the invention, in which a connection layer is applied to the top of the carrier substrate with component structures, which serves as an adhesive layer when connecting the carrier substrate to the cover plate.
  • FIG. 7 shows a development of the invention in which the connection layer is applied to the underside of the cover plate.
  • FIG. 8 shows a detail of a component according to the invention with an advantageous configuration of the plated-through holes.
  • FIG. 1 shows a known method for producing plated-through holes in a substrate SU.
  • a blind hole DE is produced in the substrate SU, for example by etching.
  • the blind hole is preferably lined with an electrically insulating layer in method step b) (in particular in the case of a semiconducting substrate SU).
  • an electrically conductive material FM is applied to the top of the substrate SU, which material also fills the blind holes DE.
  • the electrically conductive material FM is removed from the upper side of the substrate SU, the electrically conductive material FM remaining in the blind holes.
  • a contact area KF2 is formed in a metallization plane ME2 directly above the filled blind hole.
  • the substrate SU is made from the underside, for example by thinning the disks by grinding and then chemical mechanical polishing thinned until the metallization of the blind hole is exposed.
  • a connection area KF1 is formed in a metallization level ME1 directly below the via DK formed in this way.
  • the first variant of a method according to the invention is explained in FIG.
  • the first method steps, not shown here, correspond to method steps a) to d) of the method already explained in FIG. 1.
  • the layers of an acoustic mirror AK are applied one after the other on the upper side of the carrier substrate TS.
  • the layers of the acoustic mirror AK are structured, for example by etching, in such a way that at least regions of the contact areas KF2 are exposed.
  • the areas of the upper side of the carrier substrate provided for connection to the cover plate are also preferably exposed.
  • a lower electrode layer UE is first applied or structured so that an electrode is formed above the acoustic mirror AK, which is electrically connected to the contact surface KF2.
  • a structured piezoelectric layer PS is applied over the lower electrode.
  • An upper electrode layer OE is applied to the piezoelectric layer PS, in which an upper electrode is formed above the lower electrode and is electrically connected to a contact surface (not shown in this figure).
  • the layers applied to one another on the carrier substrate TS form the layers of a layer system SS.
  • the lower electrode, the piezoelectric layer and the upper electrode form a thin-film resonator RE.
  • the Resonator RE and the acoustic mirror AK together form a component structure BS.
  • the top of the carrier substrate with thin-film resonators arranged thereon is preferably covered over a large area with a trimming layer TR z. B. coated with silicon oxide, the trimming layer surrounding the component structures BS and sealingly sealed to the carrier substrate TS.
  • the trimming layer TR is used, for example, for frequency tuning of the component and here also as
  • Connection layer or adhesive layer when connecting the carrier substrate TS to the cover plate CAP is
  • the carrier substrate TS is first connected to the cover plate and only then thinned from below to form vias.
  • the cover plate CAP has a cavity AH, which faces the carrier substrate TS and, when the carrier substrate is connected to the cover plate, the component structures
  • the carrier substrate TS is thinned from its underside before it is connected to the cover plate.
  • the pocket holes DE are converted into the corresponding plated-through holes DK.
  • step d) is on the bottom of the
  • connection surfaces KF1 provided as external contacts of the component are formed.
  • the connection areas KF1 are arranged directly under the plated-through holes DK.
  • the exposed underside of a via can itself be used as a connection surface.
  • FIG. 3a shows a schematic bottom view of a large-area cover plate CAP, in which a plurality of cavities AH are formed, for example by pressing or etching, and are used for later acceptance of the component structures BS.
  • the hollows AH are preferably produced by photo technology in a wet etching process.
  • FIG. 3b shows a schematic plan view of a wafer which has arisen by connecting the large-area carrier substrate TS and the large-area cover plate CAP.
  • the cavities HR which are not visible from the outside and accommodate the component structures BS, are indicated by dashed lines.
  • the further lines TL indicate the (imaginary) dividing lines along which the components produced in parallel on the carrier substrate are separated.
  • FIG. 4 shows a method according to the invention for producing a component working with surface acoustic waves.
  • a piezoelectric layer PS is applied to the carrier substrate TS.
  • the blind holes DE are produced in the composite from the carrier substrate TS and the piezoelectric layer PS, the respective blind hole DE completely passing through the piezoelectric layer PS.
  • the blind hole DE is preferably lined with an electrically and / or thermally insulating layer IS and filled with an electrically conductive material FM.
  • the electrically conductive material FM can e.g. B. thermally deposited tungsten or an electrically conductive paste with a doctor blade.
  • a metallization layer is applied to the piezoelectric layer PS, which is provided as the second metallization level ME2.
  • this metallization layer is structured in such a way that the contact areas KF2 are formed above the blind holes DE and are electrically connected to the component structures (here, for example, converter WA) that are also formed in the second metallization level ME2.
  • the structure of the component according to the invention after method step e) is shown in a schematic cross section (above) and in a schematic top view from above (directly below).
  • connection layer VS is applied to the carrier substrate TS in the areas to be connected to the cover plate. It is also possible to alternatively apply the connection layer VS on the underside of the cover plate CAP, at least in the areas on the underside of the cover plate CAP, which are later connected to the carrier substrate TS.
  • the connection layer VS serves to hermetically seal the cavity
  • the thinning of the carrier substrate becomes only after the connection with made of the cover plate.
  • the subsequent thinning of the carrier substrate has the advantage compared to the variant of the invention, in which instead of blind holes through openings are created, that the carrier substrate initially has a (large) thickness required for processing, which later reduces to reduce the overall height of the component can be.
  • FIGS. 4 and 5 It is possible, as indicated in FIGS. 4 and 5, to apply the connecting layer VS on the piezoelectric layer PS preferably in the areas which are bonded directly with the cover plate CAP.
  • FIG. 5 also indicates that the plated-through holes DK are formed in the carrier substrate TS before the carrier substrate is connected to the cover plate.
  • the carrier substrate TS is made of semiconducting material, e.g. B. made of silicon.
  • an electrically and preferably also thermally insulating layer IS1 is arranged between the second metallization level and the carrier substrate.
  • insulating layer IS1 in conjunction with a carrier substrate made of dielectric or semiconducting material
  • another functional layer or a functional layer system can also be provided, which, for. B. serves as a connecting layer between the carrier substrate and the cover plate.
  • the functional layers can also be used
  • Frequency adjustment of the component or to compensate for different thermal expansion coefficients of the carrier substrate and the lower layers of the component structures BS are used.
  • FIG. 7 shows a further variant of the invention, in which the connection layer VS extends over a large area to that for Carrier substrate TS side of the cover plate CAP is applied.
  • FIG. 8 shows a detail of a component according to the invention, in which the through-contact DK, which connects the contact surface KF2 and the connection surface KF1, is formed from a plurality of vertical, electrically conductive connections arranged next to one another.
  • a component according to the invention is also not limited to the specified materials, to the number of elements shown or to certain frequency ranges.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Manufacture Of Switches (AREA)

Abstract

L'invention concerne la formation de connexions électriques transversales verticales dans un substrat support présentant une surface sur laquelle des structures de composant sont fixées, ces structures de composant étant reliées à des surfaces de contact placées au-dessus des connexions transversales. Les structures de composant et les surfaces de contact sont placées dans des cavités formées lors de la soudure directe du substrat support ('Direct Wafer Bonding') au moyen d'une plaque de recouvrement présentant des évidements correspondants.
PCT/EP2004/006500 2003-07-10 2004-06-16 Composant electronique et procede de fabrication WO2005006432A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2003131322 DE10331322A1 (de) 2003-07-10 2003-07-10 Elektronisches Bauelement und Verfahren zur Herstellung
DE10331322.2 2003-07-10

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Publication Number Publication Date
WO2005006432A2 true WO2005006432A2 (fr) 2005-01-20
WO2005006432A3 WO2005006432A3 (fr) 2005-04-28

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DE (1) DE10331322A1 (fr)
WO (1) WO2005006432A2 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
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WO2007055924A2 (fr) * 2005-11-03 2007-05-18 Maxim Integrated Products, Inc. Procede de boitier sur tranche
EP2017628A1 (fr) * 2007-07-20 2009-01-21 Hitachi Ltd. Capteur physique et procédé de fabrication
EP1749794A3 (fr) * 2005-08-01 2011-11-30 Shinko Electric Industries Co., Ltd. Boitier pour dispositifs électroniques et son procédé de fabrication
US9177893B2 (en) 2011-05-17 2015-11-03 Infineon Technologies Ag Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof

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TW200644165A (en) * 2005-05-04 2006-12-16 Icemos Technology Corp Silicon wafer having through-wafer vias
US7807550B2 (en) * 2005-06-17 2010-10-05 Dalsa Semiconductor Inc. Method of making MEMS wafers
JP2010514180A (ja) * 2006-12-21 2010-04-30 コンチネンタル・テベス・アーゲー・ウント・コンパニー・オーハーゲー カプセル化モジュール、その生成のための方法、およびその使用
KR100878410B1 (ko) 2007-07-11 2009-01-13 삼성전기주식회사 수정 진동자 제조방법
US9444428B2 (en) * 2014-08-28 2016-09-13 Avago Technologies General Ip (Singapore) Pte. Ltd. Film bulk acoustic resonators comprising backside vias
DE102018108611B4 (de) * 2018-04-11 2019-12-12 RF360 Europe GmbH Gehäuse für elektrische Vorrichtung und Verfahren zum Herstellen des Gehäuses

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JPH05326702A (ja) * 1992-05-14 1993-12-10 Seiko Epson Corp シリコンとガラスの接合部材の製造方法
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
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WO2002058233A1 (fr) * 2001-01-18 2002-07-25 Infineon Technologies Ag Dispositifs filtrants et procede de fabrication de ces derniers
US20020113321A1 (en) * 2001-02-22 2002-08-22 Oleg Siniaguine Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture

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US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
EP0851492A2 (fr) * 1996-12-06 1998-07-01 Texas Instruments Incorporated Structure de substrat à montage de surface et méthode
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US20020093398A1 (en) * 2001-01-16 2002-07-18 Juha Ella Bulk acoustic wave resonator with a conductive mirror
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US20020113321A1 (en) * 2001-02-22 2002-08-22 Oleg Siniaguine Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1749794A3 (fr) * 2005-08-01 2011-11-30 Shinko Electric Industries Co., Ltd. Boitier pour dispositifs électroniques et son procédé de fabrication
WO2007055924A2 (fr) * 2005-11-03 2007-05-18 Maxim Integrated Products, Inc. Procede de boitier sur tranche
WO2007055924A3 (fr) * 2005-11-03 2007-07-19 Maxim Integrated Products Procede de boitier sur tranche
US7393758B2 (en) 2005-11-03 2008-07-01 Maxim Integrated Products, Inc. Wafer level packaging process
EP2017628A1 (fr) * 2007-07-20 2009-01-21 Hitachi Ltd. Capteur physique et procédé de fabrication
US7905149B2 (en) 2007-07-20 2011-03-15 Hitachi, Ltd. Physical sensor and method of process
US9177893B2 (en) 2011-05-17 2015-11-03 Infineon Technologies Ag Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof

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WO2005006432A3 (fr) 2005-04-28

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