KR100445569B1 - Process for producing contacts on electrical components suitable for a flip-chip assembly - Google Patents

Process for producing contacts on electrical components suitable for a flip-chip assembly Download PDF

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Publication number
KR100445569B1
KR100445569B1 KR10-1998-0704406A KR19980704406A KR100445569B1 KR 100445569 B1 KR100445569 B1 KR 100445569B1 KR 19980704406 A KR19980704406 A KR 19980704406A KR 100445569 B1 KR100445569 B1 KR 100445569B1
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cover
layer
solderable
conductive structure
solderable layer
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KR10-1998-0704406A
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Korean (ko)
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KR19990072096A (en
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볼프강 팔
알로이스 슈텔출
한스 크뤼거
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지멘스 마츠시타 컴포넌츠 게엠베하 운트 콤파니 카게
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Acoustics & Sound (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 표면파 소자(OFW-소자)상에 플립-칩 어셈블리에 적합한 콘택을 제조하기 위한 방법에 관한 것으로, 기판(1)상에 제공된 도전성 구조물(3)을 커버(2)로 밀봉하고, 상기 커버(2)를 제조한 후에 도전성 구조물(3)의 패드와 접촉되는 납땜 가능한 층(4)을 제공한다.The present invention relates to a method for manufacturing a contact suitable for a flip-chip assembly on a surface wave element (OFW-element), in which a conductive structure 3 provided on a substrate 1 is sealed with a cover 2, A solderable layer (4) is provided which is in contact with the pad of the conductive structure (3) after the cover (2) is produced.

Description

플립-칩 어셈블리에 적합한 전기 소자의 콘택을 제조하기 위한 방법 {PROCESS FOR PRODUCING CONTACTS ON ELECTRICAL COMPONENTS SUITABLE FOR A FLIP-CHIP ASSEMBLY}TECHNICAL FIELD [0001] The present invention relates to a method for manufacturing a contact of an electric device suitable for a flip-chip assembly. ≪ Desc / Clms Page number 1 >

독일 특허 출원서 P 444 15 411.9호에는 기판상에 있는 소자 구조물을 폐쇄하는 캡을 갖는 전자 소자용 밀봉 방식이 기술되어 있는데, 상기 방식에서 캡은 소자 구조물의 영역에 상기 구조물을 수용하는 리세스를 포함하는, 기판상에 제공된 커버로 형성된다. 상기 방식의 밀봉은 소자 구조물을 주변 영향으로부터 보호해 주기 때문에, 상기 방식으로 밀봉된 전자 소자들은 또다른 하우징이 없어도 직접 사용할 수 있다.German patent application P 444 15 411.9 describes a sealing scheme for electronic devices having a cap which closes the device structure on the substrate, wherein the cap comprises a recess for receiving the structure in the region of the device structure A cover provided on the substrate. Electronic devices sealed in this manner can be used directly without another housing, because the sealing in this manner protects the device structure from ambient influences.

소형화 추세에 따라, 최소 하우징 체적을 요구하고 전체적인 높이가 낮은 소자를 만들기 위한 노력이 진행되어 왔다. 상기와 같은 요구들은 예를 들어 전자 소자를 전화 카드 또는 신용 카드와 같은 칩카드에 사용할 때 제기되는 것들이다. 전술한 독일 출원서에 따라 밀봉된 소자들은 상기 요구들을 최상으로 만족시킨다. 이것은 특히 상기 소자들이 플립-칩 어셈블리에 적합하게 형성되는 경우에 진실이다.With the trend toward miniaturization, efforts have been made to create a device with a minimum overall housing height and a low overall height. Such requirements are those that are raised, for example, when using electronic devices for chip cards such as telephone cards or credit cards. The sealed elements according to the above-mentioned German patent application satisfy the above requirements best. This is true especially if the elements are suitably formed in a flip-chip assembly.

지금까지 플립-칩 어셈블리에 적합한 소자들은 하나의 하우징, 특히 세라믹 하우징에 조립되었다. 상기 경우에는 소자 시스템의 접속면(즉, 패드)에 범프를 갖는 선택적으로 납땜 가능한 층들이 제공되어야 하기 때문에, 이를 위한 일련의 프로세스 단계들이 필요하다. 그러나, 표면이 중첩되는 핑거 구조물로 인해 단락 가능성이 더 커지기 때문에, 특히 SAW-소자에서는 상기 층들이 문제가 된다.Until now, elements suitable for flip-chip assembly have been assembled into one housing, especially a ceramic housing. In this case, a series of process steps are required, since selectively solderable layers with bumps must be provided on the connection side (i.e., pad) of the device system. However, these layers are problematic, especially in SAW-devices, because the possibility of shorting due to superimposed finger structures on the surface is greater.

본 발명은 청구항 1의 서문에 따른 전기 소자상에 플립-칩 어셈블리에 적합한 콘택을 제조하기 위한 방법에 관한 것이다.The present invention relates to a method for manufacturing a contact suitable for a flip-chip assembly on an electrical element according to the preamble of claim 1.

도 1은 본 발명에 따른 방법으로 제조된 SAW-소자의 개략도이고,1 is a schematic view of a SAW-device fabricated by a method according to the present invention,

도 2는 도 1에 따른 소자를 부분적으로 도시한 평면도이다.Fig. 2 is a plan view partially showing the element according to Fig. 1; Fig.

본 발명의 목적은, 소자 구조물을 손상시키지 않으면서, 플립-칩 어셈블리에 적합한 콘택을 위한 납땜 가능한 층을 제조할 수 있는 방법을 제공하는 것이다.It is an object of the present invention to provide a method of manufacturing a solderable layer for a contact suitable for a flip-chip assembly, without damaging the device structure.

상기 목적은, 서문에 언급된 방식의 방법에서 본 발명에 따른 청구항 1의 특징부의 특징에 의해 달성된다.This object is achieved by a feature of the feature of claim 1 according to the invention in a method in the manner mentioned in the preamble.

본 발명의 개선예는 종속항의 대상이다.The improvements of the invention are subject to the dependent claims.

본 발명은 도면에 따른 실시예를 참조하여 하기에 자세히 설명된다.The invention is described in detail below with reference to an embodiment according to the drawings.

탄성 표면파 소자(SAW-소자)는 일반적으로 도 1에 따라 압전 기판(1) 및 그 위에 제공된 도전성 구조물(3)로 이루어지며, 상기 구조물은 예를 들어 인터디지털 변환기, 공진기 또는 반사기의 전극 핑거이다. 서문에 언급된 독일 특허 출원서에기술된 바와 같이, 도전성 구조물(3)은 상기 구조물을 주변 영향에 대해 보호해 주는 캡(2)에 의해 커버되고, 소자는 캡(2) 및 기판(1)과 함께 "하우징"으로서 직접 사용될 수 있다.The SAW device generally comprises a piezoelectric substrate 1 and a conductive structure 3 provided thereon according to Fig. 1, and the structure is, for example, an electrode finger of an interdigital transducer, a resonator, or a reflector . As described in the German patent application referred to in the preamble, the conductive structure 3 is covered by a cap 2 which protects the structure against ambient influences, and the device comprises a cap 2 and a substrate 1, Can be used directly as a " housing ".

본 발명에 따르면, 플립-칩 어셈블리에 적합한 콘택은 도전성 구조물(3)을 전기적으로 콘택팅하기 위해 제공된다. 도 1에 개략적으로 도시된 바와 같이, 커버(2)내에는 윈도우(6)가 제공되고, 상기 윈도우를 통해 납땜 가능한 층(4)이 제공되며, 상기 납땜 가능한 층은 도전성 구조물(3)의 (도시되지 않은) 접속면, 즉 패드와 접촉되어 있다. 이 경우 납땜 가능한 층(4)은 도 2에서 알 수 있는 바와 같이 커버(2) 부분상에도 배치된다. 납땜 가능한 층은 예컨대 크롬/크롬구리/구리/골드층이다.According to the present invention, a suitable contact for the flip-chip assembly is provided for electrically contacting the conductive structure 3. 1, a window 6 is provided in a cover 2, through which a solderable layer 4 is provided, the solderable layer being provided on the surface of the conductive structure 3 (Not shown), i.e., a pad. In this case, the solderable layer 4 is also arranged on the part of the cover 2 as seen in Fig. The solderable layer is, for example, a chromium / chromium copper / copper / gold layer.

본 발명의 실시예에 따라 납땜 가능한 층을 제조하기 위해서는 제일 먼저 납땜 가능한 재료로 이루어진 층을 전표면적으로, 즉 전체 커버(2)상에 기상증착 후, 각각 도전성 구조물(3)의 패드와 각각 접촉되어 있는 납땜 가능한 개별 층(4)이 얻어지도록 상기 커버를 구조화한다.In order to manufacture the solderable layer according to the embodiment of the present invention, first, a layer made of a material that can be soldered is vapor-deposited on the entire cover 2, that is, on the entire cover 2, The cover is structured so as to obtain an individual solderable layer (4).

다른 실시예에 따르면, 납땜 가능한 층(4)은 층의 치수를 결정해주는 마스크를 통해서도 기상증착될 수 있다.According to another embodiment, the solderable layer 4 may also be vapor deposited via a mask that determines the dimensions of the layer.

납땜 가능한 층을 제조한 후에는, 납땜 가능 층(4)과 접촉되는 범프(7)를 윈도우(6)내에 제공하여 상기 층(4)과 납땜한다. 상기 범프(7)를 통해 소자가 전자 회로에 장착될 수 있다.After manufacturing the solderable layer, a bump 7 in contact with the solderable layer 4 is provided in the window 6 and soldered to the layer 4. The device can be mounted on the electronic circuit via the bumps 7.

본 발명에 따른 방법의 장점은, 소자 구조물을 주변 영향에 대해 보호해주는커버(2)를 제공한 다음에 비로서 납땜 가능한 층(4) 및 범프(7)를 제조한다는 점이다. 그럼으로써, 납땜 가능한 층 및 범프 제조시의 방법 단계들에서 나타나는 영향들로 인해 소자 구조물이 더 이상 손상을 받지 않게 된다. 다른 장점으로서는, 납땜 가능한 층들을 넓은 표면에 걸쳐서 제조할 수 있으므로, 상기 납땜 가능한 층들의 치수가 (도시되지 않은) 패드의 치수에 비해서 크다는 점이다.An advantage of the method according to the present invention is that it provides a cover 2 that protects the device structure against ambient influences, and then manufactures the solderable layer 4 and the bumps 7. Thereby, the effects of the solderable layer and the method steps in the manufacture of the bump cause the device structure to no longer be damaged. Another advantage is that the dimensions of the solderable layers are large relative to the dimensions of the pad (not shown), since the solderable layers can be manufactured over a large surface.

윈도우가 도전층(4)을 위해 마스크로서 작용하는 동시에 마스크의 가장자리에서 기상증착이 이루어지지 않도록 윈도우(6)를 커버(2)내에 형성함으로써, 전표면적으로 기상증착된 층(4)의 구조화가 피해진다.By forming the window 6 in the cover 2 so that the window acts as a mask for the conductive layer 4 and vapor deposition is not made at the edges of the mask, the structuring of the vapor deposited layer 4 with the total area It is avoided.

Claims (4)

음향 표면파로 동작하는 SAW-소자상에 플립 칩 어셈블리에 적합한 콘택을 제조하는 방법에서, 기판(1)상에 제공된 도전성 구조물(3)은 상기 도전성 구조물(3)의 영역에서 상기 구조물을 수용하는 리세스를 포함하는 캡형 커버(2)에 의해 공동부내에서 주변 환경에 대해 밀봉되고, 상기 커버에는 윈도우(6)가 제공되며, 상기 도전성 구조물(3)은 접속면을 갖도록 구성되는, 상기 콘택 제조 방법으로서,In a method for manufacturing a contact suitable for a flip chip assembly on a SAW-element operating with acoustic surface waves, a conductive structure 3 provided on a substrate 1 is provided with a conductive layer 3 for receiving the structure in the region of the conductive structure 3 Wherein the cover is sealed to a surrounding environment in a cavity by a cap-like cover (2) including a sieve, the cover (6) being provided and the conductive structure (3) As a result, 기판상에 커버(2)를 형성하는 단계Forming a cover (2) on a substrate -상기 커버는 리세스를 가짐-;The cover has a recess; 납땜 가능한 재료로 이루어진 층을 전표면적으로 기상 증착하는 단계; 및Vapor-depositing a layer made of a solderable material to a surface area; And 상기 납땜 가능한 층(4)을 형성하기 위해 상기 기상 증착된 층을 구조화하는 단계를 포함하고,And structuring said vapor deposited layer to form said solderable layer (4) 상기 납땜 가능한 층의 치수는 상기 접속면의 치수에 비해 크고, 상기 납땜 가능한 층은 윈도우내에서 상기 접속면과 전기적으로 접속되는 콘택 제조 방법.Wherein the dimension of the solderable layer is larger than the dimension of the contact surface and the solderable layer is electrically connected to the contact surface within the window. 음향 표면파로 동작하는 SAW-소자상에 플립 칩 어셈블리에 적합한 콘택을 제조하는 방법에서, 기판(1)상에 제공된 도전성 구조물(3)은 상기 도전성 구조물(3)의 영역에서 상기 구조물을 수용하는 리세스를 포함하는 캡형 커버(2)에 의해 공동부내에서 주변 환경에 대해 밀봉되고, 상기 커버에는 윈도우(6)가 제공되며, 상기 도전성 구조물(3)은 접속면을 갖도록 구성되는, 상기 콘택 제조 방법으로서,In a method for manufacturing a contact suitable for a flip chip assembly on a SAW-element operating with acoustic surface waves, a conductive structure 3 provided on a substrate 1 is provided with a conductive layer 3 for receiving the structure in the region of the conductive structure 3 Wherein the cover is sealed to a surrounding environment in a cavity by a cap-like cover (2) including a sieve, the cover (6) being provided and the conductive structure (3) As a result, 기판상에 커버(2)를 형성하는 단계Forming a cover (2) on a substrate -상기 커버는 리세스를 가짐-;The cover has a recess; 상기 커버상에 마스크를 형성하는 단계; 및Forming a mask on the cover; And 납땜 가능한 층(4)을 형성하기 위해 납땜 가능한 재료로 이루어진 하나의 층을 마스크를 통해 전표면적으로 기상 증착하는 단계를 포함하고,Vapor-depositing one layer of a solderable material through a mask to a surface area to form a solderable layer (4) 상기 납땜 가능한 층의 치수는 상기 접속면의 치수에 비해 크고, 상기 납땜 가능한 층은 윈도우내에서 상기 접속면과 전기적으로 접속되는 콘택 제조 방법.Wherein the dimension of the solderable layer is larger than the dimension of the contact surface and the solderable layer is electrically connected to the contact surface within the window. 제 1항 또는 제 2항에 있어서, 상기 납땜 가능한 층(4)과 접촉되는 범프(7)를 커버(2)내에 있는 윈도우내에 제공하는 것을 특징으로 하는 방법.3. Method according to claim 1 or 2, characterized in that a bump (7) in contact with the solderable layer (4) is provided in a window in the cover (2). 제 1항 또는 제 2항에 있어서, 상기 납땜 가능한 층(4)을 전표면적으로 기상증착하고, 이 경우 도전성 구조물(3)의 접속면상에 배치된 납땜 가능한 층(4)의 부분이 커버(2)상에 배치된 납땜 가능한 층(4)의 부분과 도통되지 않도록 커버(2)를 마스크로서 사용하는 것을 특징으로 하는 방법.The method according to claim 1 or 2, wherein the solderable layer (4) is vapor-deposited with a surface area, wherein a portion of the solderable layer (4) disposed on the connection surface of the conductive structure (3) Wherein the cover (2) is used as a mask so as not to be electrically conductive with a portion of the solderable layer (4) disposed on the cover (2).
KR10-1998-0704406A 1995-12-21 1996-12-16 Process for producing contacts on electrical components suitable for a flip-chip assembly KR100445569B1 (en)

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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19806550B4 (en) 1998-02-17 2004-07-22 Epcos Ag Electronic component, in particular component working with surface acoustic waves - SAW component
DE19806818C1 (en) 1998-02-18 1999-11-04 Siemens Matsushita Components Method for producing an electronic component, in particular an SAW component working with acoustic surface waves
DE19822794C1 (en) 1998-05-20 2000-03-09 Siemens Matsushita Components Multiple uses for electronic components, in particular surface acoustic wave components
KR100687548B1 (en) * 1999-01-27 2007-02-27 신꼬오덴기 고교 가부시키가이샤 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
US6747298B2 (en) * 2001-07-23 2004-06-08 Cree, Inc. Collets for bonding of light emitting diodes having shaped substrates
US6888167B2 (en) * 2001-07-23 2005-05-03 Cree, Inc. Flip-chip bonding of light emitting devices and light emitting devices suitable for flip-chip bonding
DE10142542A1 (en) * 2001-08-30 2003-03-27 Infineon Technologies Ag Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier
DE10302298A1 (en) 2003-01-22 2004-08-05 Henkel Kgaa Heat-curable, thermally expandable composition with a high degree of expansion
US6992400B2 (en) * 2004-01-30 2006-01-31 Nokia Corporation Encapsulated electronics device with improved heat dissipation
US7608789B2 (en) * 2004-08-12 2009-10-27 Epcos Ag Component arrangement provided with a carrier substrate
DE102005008512B4 (en) 2005-02-24 2016-06-23 Epcos Ag Electrical module with a MEMS microphone
DE102005008514B4 (en) * 2005-02-24 2019-05-16 Tdk Corporation Microphone membrane and microphone with the microphone membrane
DE102005008511B4 (en) * 2005-02-24 2019-09-12 Tdk Corporation MEMS microphone
JP4585419B2 (en) 2005-10-04 2010-11-24 富士通メディアデバイス株式会社 Surface acoustic wave device and manufacturing method thereof
DE102005053767B4 (en) * 2005-11-10 2014-10-30 Epcos Ag MEMS microphone, method of manufacture and method of installation
DE102005053765B4 (en) * 2005-11-10 2016-04-14 Epcos Ag MEMS package and method of manufacture
JP4881211B2 (en) * 2007-04-13 2012-02-22 新光電気工業株式会社 Wiring substrate manufacturing method, semiconductor device manufacturing method, and wiring substrate
DE102013106353B4 (en) * 2013-06-18 2018-06-28 Tdk Corporation Method for applying a structured coating to a component
US10431533B2 (en) * 2014-10-31 2019-10-01 Ati Technologies Ulc Circuit board with constrained solder interconnect pads

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645807A1 (en) * 1993-04-08 1995-03-29 Citizen Watch Co. Ltd. Semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59172756A (en) * 1983-03-22 1984-09-29 Nec Corp Semiconductor device
GB2171850B (en) * 1985-02-22 1988-05-18 Racal Mesl Ltd Mounting surface acoustic wave components
JPS62173814A (en) * 1986-01-28 1987-07-30 Alps Electric Co Ltd Mounting unit for surface acoustic wave element
JP2563652B2 (en) * 1990-07-17 1996-12-11 株式会社東芝 Semiconductor device and manufacturing method thereof
EP0475139A3 (en) * 1990-09-04 1992-03-25 Motorola, Inc. Method and apparatus for saw device passivation
JPH0590872A (en) * 1991-09-27 1993-04-09 Sumitomo Electric Ind Ltd Surface acoustic wave element
JP2718854B2 (en) * 1992-06-10 1998-02-25 株式会社東芝 Semiconductor device
EP0590780B1 (en) * 1992-08-28 1997-06-25 Dow Corning Corporation Method for producing an integrated circuit with hermetic protection based on a ceramic layer
DE4302171A1 (en) * 1993-01-22 1994-07-28 Be & We Beschaeftigungs Und We Surface acoustic wave component mfr. with chip and support

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0645807A1 (en) * 1993-04-08 1995-03-29 Citizen Watch Co. Ltd. Semiconductor device

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