DE10142542A1 - Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier - Google Patents

Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier

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Publication number
DE10142542A1
DE10142542A1 DE10142542A DE10142542A DE10142542A1 DE 10142542 A1 DE10142542 A1 DE 10142542A1 DE 10142542 A DE10142542 A DE 10142542A DE 10142542 A DE10142542 A DE 10142542A DE 10142542 A1 DE10142542 A1 DE 10142542A1
Authority
DE
Germany
Prior art keywords
chip
semiconductor chip
arrangement according
chip carrier
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE10142542A
Other languages
German (de)
Inventor
Bernhard Schulte-Doeinghaus
Kai Geyer
Harald Gundlach
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10142542A priority Critical patent/DE10142542A1/en
Priority to PCT/DE2002/003147 priority patent/WO2003026006A2/en
Publication of DE10142542A1 publication Critical patent/DE10142542A1/en
Withdrawn legal-status Critical Current

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The arrangement has the semiconductor chip (1) mounted on the chip carrier (2) and enclosed by a resin mass (3) or an insulation layer, before application of a conductive coating (4) to the opposite side of the semiconductor chip to the chip carrier, in the form of a conductive layer applied to the resin mass or insulation layer and connected to a metal layer (7) applied to the chip carrier, e.g. a low-pass filter layer. Also included are Independent claims for the following: (a) a chip card; (b) a chip module

Description

Die vorliegende Erfindung betrifft die Anordnung eines Halbleiterchips in einem Gehäuse, mit der eine elektromagnetische Emission oder Immission des Halbleiterchips verhindert wird, sowie eine damit ausgestattete Chipkarte oder ein Chipmodul. The present invention relates to the arrangement of a Semiconductor chips in a package with which an electromagnetic Emission or immission of the semiconductor chip is prevented, and a chip card or chip module equipped with it.

In der Zukunft können bei UICC (universal integrated circuit card), insbesondere bei Chipkarten (smart cards) vermehrt elektromagnetische Störungen infolge hoher im Betrieb auftretender Frequenzen, insbesondere digitaler Schaltungen, auftreten. Die im Betrieb der Schaltung vorhandenen elektrischen Ströme und Spannungen sind die Ursache für das Auftreten der Abstrahlung hochfrequenter elektromagnetischer Wellen, die auch durch die vorhandenen elektrischen Leiter geführt sein können. Zunehmend höhere interne Taktraten bei den integrierten Schaltkreisen sind die Ursache für die Erzeugung stärkerer elektromagnetischer Felder. Es ist daher mit vermehrten Störeinflüssen zu rechnen, die sich ausgehend von dem Halbleiterchip auch auf ein Gerät, in dem der Halbleiterchip eingesetzt ist, auswirken (Terminal, Handy und dergleichen). In the future, UICC (universal integrated circuit card), especially with smart cards electromagnetic interference due to high in operation occurring frequencies, especially digital circuits, occur. The electrical existing in the operation of the circuit Currents and voltages are the cause of the occurrence of the Radiation of high-frequency electromagnetic waves, the also be led through the existing electrical conductors can. Increasingly higher internal clock rates for the Integrated circuits are the cause of the generation stronger electromagnetic fields. It is therefore with increased Interferences to be expected, starting from the Semiconductor chip also on a device in which the semiconductor chip used, impact (terminal, cell phone and the like).

Aufgabe der vorliegenden Erfindung ist es, eine Möglichkeit zur Verminderung der Störeinflüsse durch hochfrequente elektromagnetische Abstrahlung von Halbleiterchips anzugeben. The object of the present invention is a possibility to reduce interference caused by high-frequency Specify electromagnetic radiation from semiconductor chips.

Diese Aufgabe wird mit der Anordnung eines Halbleiterchips in einem Gehäuse mit den Merkmalen des Anspruches 1 bzw. des Anspruches 5 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen. This task is accomplished with the arrangement of a semiconductor chip in a housing with the features of claim 1 and Claim 5 solved. Refinements result from the dependent claims.

Bei dieser Anordnung besitzt das Gehäuse eine rings umgebende Abschirmung nach Art eines Faraday'schen Käfigs; oder es sind geeignete Dämpfungselemente in den Zuleitungen vorgesehen; es können auch gleichzeitig diese beiden Mittel eingesetzt sein. Auf diese Weise kann insbesondere ein Chipkarten-Modul-Gehäuse mit einer Abschirmung versehen sein. Die Anordnung kann auch direkt in einer Smart-Card oder einer UICC eingesetzt sein. In this arrangement, the housing has a surrounding Shielding in the manner of a Faraday cage; or there are suitable damping elements are provided in the feed lines; it these two agents can also be used simultaneously. In this way, a Chip card module housing can be provided with a shield. The arrangement can also used directly in a smart card or a UICC his.

Es folgt eine genauere Beschreibung von Beispielen dieser Anordnung an Hand der Fig. 1 bis 3. The following is a more detailed description of examples of this arrangement with reference to FIGS. 1 to 3.

Die Fig. 1 und 2 zeigen jeweils ein Ausführungsbeispiel einer Anordnung eines Halbleiterchips in einem Gehäuse. Figs. 1 and 2 each show an example of an arrangement of a semiconductor chip in a housing.

Die Fig. 3 zeigt die Ausgestaltung einer als Filter vorgesehenen Leiterbahnspirale. Fig. 3 shows the configuration of a filter provided as a conductor spiral.

In der Fig. 1 ist ein erstes Ausführungsbeispiel einer Anordnung eines Halbleiterchips 1 in einem Gehäuse im Querschnitt dargestellt. Es ist ein Chipträger 2 vorhanden, auf dem der Chip, in diesem Beispiel mittels einer Anzahl von Flächen aus einem Silberleitkleber 11, angebracht ist. Der Chipträger und der Chip sind mit einer Vergussmasse 3 (Mold, Globetop) verkapselt. Auf der äußeren Oberseite der Vergussmasse 3, d. h. auf der von dem Halbleiterchip 1 abgewandten Außenseite, ist eine elektrisch leitende Beschichtung 4 vorhanden. Der Chipträger 2 ist mit elektrischen Leitern versehen, die in diesem Beispiel Anschlussleiter 5 umfassen, die für einen externen elektrischen Anschluss vorgesehen sind. Diese Leiter befinden sich auf der üblicherweise als Vorderseite des gehäusten Chips bezeichneten, von dem Halbleiterchip abgewandten Oberseite des Chipträgers, die in der in der Fig. 1 dargestellten Orientierung unten ist. Es sind Durchbrüche 9, 10 durch den Chipträger 2 vorhanden, die z. B. zylindrische Löcher sein können. Durch diese Durchbrüche hindurch sind Bonddrähte 8 geführt, die die Anschlussleiter 5 mit Anschlusskontakten 6 des Halbleiterchips 1 elektrisch leitend verbinden. In Fig. 1 a first embodiment of an arrangement of a semiconductor chip 1 is shown in a housing in cross section. There is a chip carrier 2 on which the chip is attached, in this example by means of a number of surfaces made of a silver conductive adhesive 11 . The chip carrier and the chip are encapsulated with a sealing compound 3 (mold, globetop). An electrically conductive coating 4 is present on the outer top of the potting compound 3 , ie on the outside facing away from the semiconductor chip 1 . The chip carrier 2 is provided with electrical conductors, which in this example comprise connection conductors 5 , which are provided for an external electrical connection. These conductors are located on the top side of the chip carrier, which is usually referred to as the front side of the packaged chip and faces away from the semiconductor chip and which is at the bottom in the orientation shown in FIG. 1. There are openings 9 , 10 through the chip carrier 2 , the z. B. can be cylindrical holes. Bond wires 8 are guided through these openings, which connect the connecting conductors 5 to the connecting contacts 6 of the semiconductor chip 1 in an electrically conductive manner.

Vorzugsweise befindet sich auf der mit dem Halbleiterchip versehenen Rückseite des Chipträgers 2 eine Metallschicht 7, die elektrisch leitend mit den Leitern auf der Vorderseite verbunden ist. Dafür ist in dem Beispiel der Fig. 1 die mindestens eine Durchkontaktierung 12 auf der Wandung des Durchbruchs 10 vorhanden. Die Beschichtung 4 auf der Oberseite der Vergussmasse 3 ist in diesem Beispiel mit dieser Metallschicht 7 verbunden, so dass hier eine den Halbleiterchip 1 rings umgebende Abschirmung als Faraday-Käfig gebildet ist. Bei bevorzugten Ausgestaltungen ist der Anteil der Metallisierung 7, der mit der elektrisch leitenden Beschichtung 4 verbunden ist, auf Masse gelegt. Die Anschlussleiter 5 auf der Vorderseite der Anordnung sind so strukturiert, dass sie trotz Vorhandenseins der Durchkontaktierung 12 nicht über die Metallschicht 7 miteinander kurzgeschlossen sind. Die Anschlusskontakte 6 des Halbleiterchips 1 besitzen so elektrisch voneinander isolierte separate externe Anschlüsse. Andererseits wird eine weitgehende Abschirmung des Halbleiterchips auch von der Vorderseite des Gehäuses bewirkt. Von dem Halbleiterchip 1 im Betrieb der integrierten Schaltung ausgesandte elektromagnetische Störstrahlung kann so weitgehend abgeschirmt werden. A metal layer 7 , which is connected in an electrically conductive manner to the conductors on the front side, is preferably located on the rear side of the chip carrier 2 provided with the semiconductor chip. For this purpose, in the example of FIG. 1, the at least one via 12 is provided on the wall of the opening 10 . In this example, the coating 4 on the top of the casting compound 3 is connected to this metal layer 7 , so that here a shield surrounding the semiconductor chip 1 is formed as a Faraday cage. In preferred configurations, the portion of the metallization 7 which is connected to the electrically conductive coating 4 is grounded. The connection conductors 5 on the front side of the arrangement are structured such that they are not short-circuited to one another via the metal layer 7 despite the presence of the through-connection 12 . The connection contacts 6 of the semiconductor chip 1 thus have separate external connections that are electrically insulated from one another. On the other hand, the semiconductor chip is also largely shielded from the front of the housing. Electromagnetic interference radiation emitted by the semiconductor chip 1 during operation of the integrated circuit can thus be largely shielded.

Bei dem Ausführungsbeispiel gemäß Fig. 2 ist der Halbleiterchip 1 mit der mit den Anschlusskontakten 6 versehenen Oberseite nach unten auf dem Chipträger 2 nach Art einer Flip- Chip-Montage angebracht. Die Metallschicht 7 ist zu diesem Zweck geeignet strukturiert, so dass die Anschlusskontakte 6 getrennt voneinander über die jeweils vorhandenen Durchkontaktierungen 13 mit den vorgesehenen Anschlussleitern 5 auf der gegenüberliegenden Seite des Chipträgers 2 elektrisch leitend verbunden sind. Auf der von dem Chipträger 2 abgewandten Seite des Halbleiterchips ist eine elektrisch leitende Beschichtung 4 vorhanden, die vorzugsweise auf der Außenseite einer den Halbleiterchip abdeckenden Isolationsschicht 30 aufgebracht ist. Auch bei diesem Ausführungsbeispiel ist die Beschichtung vorteilhaft mit der Metallschicht 7verbunden, so dass eine auf demselben Potenzial liegende allseitige Abschirmung des Halbleiterchips 1 bewirkt ist. In the embodiment according to FIG. 2, the semiconductor chip 1 is mounted with the provided with the terminal contacts 6 upside down on the chip carrier 2 in the manner of a flip-chip mounting. The metal layer 7 is suitably structured for this purpose, so that the connection contacts 6 are electrically conductively connected separately from one another via the respective plated-through holes 13 to the provided connection conductors 5 on the opposite side of the chip carrier 2 . On the side of the semiconductor chip facing away from the chip carrier 2 there is an electrically conductive coating 4 , which is preferably applied on the outside of an insulation layer 30 covering the semiconductor chip. In this exemplary embodiment too, the coating is advantageously connected to the metal layer 7 , so that all-round shielding of the semiconductor chip 1 which is at the same potential is brought about.

Die elektrisch leitende Beschichtung 4 kann z. B. eine auf die Vergussmasse 3 beziehungsweise, falls vorhanden, die Isolationsschicht 30 aufgebrachte dünne Metallisierung sein. Es kann sich dabei auch um einen elektrisch leitenden Lack handeln, der beispielsweise durch Eintauchen der Anordnung in ein entsprechendes Bad aufgebracht wird. Es wird dabei vermieden, dass die separaten Anschlüsse durch den aufgebrachten Lack kurzgeschlossen werden. Dazu wird darauf geachtet, dass vor dem Auftragen des elektrisch leitenden Lacks alle leitenden Flächen (Chip und Drähte) abgedeckt sind, wie dies bei Globe-Top-Gehäusen oder Mold-Gehäusen ohnedies der Fall ist. Bei Flip-Chip-Gehäusen kann hierzu vor dem Lack eine nichtleitende Beschichtung aufgetragen werden, vorzugsweise in Gestalt einer Isolationsschicht 30. Die Metallschicht 7 kann grundsätzlich weggelassen sein. Insbesondere bei einer Anordnung des Chips in Flip-Chip-Technologie entsprechend der Fig. 2 ist jedoch die Metallschicht 7 besonders geeignet und schirmt die in dem Halbleiterchip integrierte Schaltung besonders gut ab. The electrically conductive coating 4 can, for. B. on the sealing compound 3 or, if present, the insulation layer 30 applied thin metallization. It can also be an electrically conductive lacquer which is applied, for example, by immersing the arrangement in a corresponding bath. It is avoided that the separate connections are short-circuited by the applied paint. For this purpose, care is taken to ensure that all conductive surfaces (chip and wires) are covered before applying the electrically conductive lacquer, as is the case with globe-top housings or mold housings anyway. In the case of flip-chip housings, a non-conductive coating can be applied for this purpose, preferably in the form of an insulation layer 30 . The metal layer 7 can in principle be omitted. In particular when the chip is arranged in flip-chip technology according to FIG. 2, however, the metal layer 7 is particularly suitable and shields the circuit integrated in the semiconductor chip particularly well.

Auftretende so genannte Kontakt-Emissionen des Chips können durch geeignete Filter in den Zuleitungen abgeschirmt werden. Derartige Kontakt-Emissionen sind hochfrequente elektromagnetische Störungen, die über die Kontakte und Zuleitungen ausgekoppelt werden. Es können hochfrequente Störungen von den Anschlusskontakten 6 des Chips über die externen Anschlussleiter 5 und beim Einsatz des Chips in einer UICC über die externen Anschlussleiter und Kontakte der Karte auch weiter bis in ein Terminal hinein weitergeleitet werden. Any so-called contact emissions of the chip can be shielded by suitable filters in the supply lines. Such contact emissions are high-frequency electromagnetic interference that are coupled out via the contacts and feed lines. High-frequency interference can also be forwarded from the connection contacts 6 of the chip via the external connection conductors 5 and, when the chip is used in a UICC, via the external connection conductors and contacts of the card into a terminal.

Die Ausbreitung störender Frequenzen kann behindert werden, indem in die Zuleitungen ein Tiefpass-Filter eingebaut wird. Ein solches Tiefpass-Filter ist zum Beispiel durch eine als Induktivität wirkende Leiterspule oder Leiterspirale gegeben. The spread of interfering frequencies can be hindered by installing a low-pass filter in the supply lines. Such a low-pass filter is, for example, by an as Given inductance acting conductor coil or conductor spiral.

Eine solche Induktivität kann insbesondere in einer der Metallschichten vorgesehen sein, mit denen die Hauptseiten des Chipträgers 2 beschichtet sind. Bei bevorzugten Ausführungsbeispielen, bei denen die Innenseite des Gehäuses mit der Metallschicht 7 auf der dem Halbleiterchip 1 zugewandten Oberseite des Chipträgers 2 beschichtet ist, kann die Induktivität in dieser Metallschicht 7 ausgebildet sein. Das geschieht z. B. in der in der Fig. 3 im Schema dargestellten Weise. Such an inductance can be provided in particular in one of the metal layers with which the main sides of the chip carrier 2 are coated. In preferred exemplary embodiments, in which the inside of the housing is coated with the metal layer 7 on the upper side of the chip carrier 2 facing the semiconductor chip 1 , the inductance can be formed in this metal layer 7 . This happens e.g. B. in the manner shown in Fig. 3 in the scheme.

In der Fig. 3 ist eine spiralartig strukturierte Leiterbahn dargestellt, die von einer Anschlussfläche 14 bis zu einer im Inneren vorhandenen weiteren Fläche verläuft, unterhalb der sich z. B. eine hier als verdeckte Kontur gestrichelt eingezeichnete Durchkontaktierung 13 durch den Chipträger 2 hindurch befindet. Auf der Anschlussfläche 14 kann z. B. nach Art einer Flip-Chip-Montage ein Anschlusskontakt 6 des Halbleiterchips 1 aufgebracht werden. Dieser Anschlusskontakt 6 wird daher nicht wie in dem in der Fig. 2 dargestellten Ausführungsbeispiel geradlinig mit der Durchkontaktierung 13 verbunden, sondern über die in der Fig. 3 als Induktivität wirkende strukturierte Leiterbahn. Bei geeigneter Dimensionierung und Strukturierung des Leiters ist so eine Filterwirkung gegen hochfrequente störende Kontakt-Emissionen erreicht. In Fig. 3, a spirally structured conductor track is shown, which extends from a connection surface 14 to a further surface inside, below which z. B. a plated-through hole 13 shown here as a hidden contour is located through the chip carrier 2 . On the pad 14 , for. B. in the manner of a flip-chip assembly, a connection contact 6 of the semiconductor chip 1 can be applied. This connection contact 6 is therefore not connected in a straight line to the plated-through hole 13 as in the exemplary embodiment shown in FIG. 2, but rather via the structured conductor track which acts as an inductor in FIG. 3. With suitable dimensioning and structuring of the conductor, a filter effect against high-frequency interfering contact emissions is achieved.

Falls die störenden Frequenzen sehr hoch sind, kann es bereits genügen, die Zuleitungen des Chips in einem geringen Abstand zueinander zu platzieren. Bei den hohen Frequenzen genügt das Übersprechen zwischen diesen Leiterbahnen bereits, um eine ausreichende Filterwirkung der hohen Frequenzen zu bewirken. Im Einzelfall kann es auch genügen, beim Vorsehen einer Spirale oder Spule als Induktivität nur eine geringe Anzahl von Windungen auszubilden, diese Windungen aber in sehr engem Abstand zueinander herzustellen. Bezugszeichenliste 1 Halbleiterchip
2 Chipträger
3 Vergussmasse
4 Beschichtung
5 Anschlussleiter
6 Anschlusskontakt
7 Metallschicht
8 Bonddraht
9 Durchbruch
10 Durchbruch
11 Silberleitkleber
12 Durchkontaktierung
13 Durchkontaktierung
14 Anschlussfläche
30 Isolationsschicht
If the interfering frequencies are very high, it may be sufficient to place the leads of the chip at a short distance from one another. At the high frequencies, the crosstalk between these interconnects is sufficient to achieve a sufficient filtering effect of the high frequencies. In individual cases, it may also suffice to form only a small number of turns when providing a spiral or coil as an inductor, but to produce these turns at a very close distance from one another. REFERENCE LIST 1 semiconductor chip
2 chip carriers
3 potting compound
4 coating
5 connection conductors
6 connection contact
7 metal layer
8 bond wire
9 breakthrough
10 breakthrough
11 conductive silver adhesive
12 through-plating
13 through-plating
14 connection surface
30 insulation layer

Claims (13)

1. Anordnung eines Halbleiterchips in einem Gehäuse, das einen Chipträger (2) umfasst, wobei
der Halbleiterchip (1) auf dem Chipträger (2) angebracht ist,
dadurch gekennzeichnet, dass
auf einer von dem Chipträger (2) abgewandten Seite des Halbleiterchips (1) eine elektrisch leitende Beschichtung (4) vorhanden ist. 1. Arrangement of a semiconductor chip in a housing, which comprises a chip carrier ( 2 ), wherein
is attached to the semiconductor chip (1) on the chip carrier (2),
characterized in that
an electrically conductive coating (4) is present on a side facing away from the chip carrier (2) side of the semiconductor chip (1). 2. Anordnung nach Anspruch 1, bei der
auf der von dem Chipträger (2) abgewandten Seite des Halbleiterchips (1) eine Vergussmasse (3) oder eine Isolationsschicht (30) vorhanden ist und
die elektrisch leitende Beschichtung (4) auf einer von dem Halbleiterchip (1) abgewandten Außenseite der Vergussmasse (3) beziehungsweise der Isolationsschicht (30) aufgebracht ist. 2. Arrangement according to claim 1, in which
on the side facing away from the chip carrier (2) side of the semiconductor chip (1) a sealing compound (3) or an insulating layer (30) is present and
the electrically conductive coating ( 4 ) is applied to an outside of the casting compound ( 3 ) or the insulation layer ( 30 ) facing away from the semiconductor chip ( 1 ). 3. Anordnung nach Anspruch 1 oder 2, bei der die Beschichtung (4) ein Lack ist. 3. Arrangement according to claim 1 or 2, wherein the coating ( 4 ) is a lacquer. 4. Anordnung nach einem der Ansprüche 1 bis 3, bei der die Beschichtung (4) mit einem elektrisch leitenden Teil des Chipkörpers (2) verbunden ist. 4. Arrangement according to one of claims 1 to 3, wherein the coating ( 4 ) with an electrically conductive part of the chip body ( 2 ) is connected. 5. Anordnung nach einem der Ansprüche 1 bis 4, bei der die Beschichtung (4) mit einem als Masseanschluss vorgesehenen Leiter des Gehäuses verbunden ist. 5. Arrangement according to one of claims 1 to 4, wherein the coating ( 4 ) is connected to a conductor of the housing provided as a ground connection. 6. Anordnung eines Halbleiterchips in einem Gehäuse, das einen Chipträger (2) mit Anschlussleitern (5) umfasst, die für externen elektrischen Anschluss vorgesehen sind, dadurch gekennzeichnet, dass mindestens eine elektrisch leitende Verbindung eines Anschlusskontaktes (6) des Halbleiterchips (1) mit einem dieser Anschlussleiter (5) des Chipträgers (2) vorhanden ist und diese Verbindung mit einem Tiefpass-Filter versehen ist. 6. Arrangement of a semiconductor chip in a housing, which comprises a chip carrier ( 2 ) with connection conductors ( 5 ) which are provided for external electrical connection, characterized in that at least one electrically conductive connection of a connection contact ( 6 ) of the semiconductor chip ( 1 ) with one of these connection conductors ( 5 ) of the chip carrier ( 2 ) is present and this connection is provided with a low-pass filter. 7. Anordnung nach Anspruch 6, bei der das Tiefpass-Filter eine als Induktivität vorgesehene spulenartige Ausbildung der elektrisch leitenden Verbindung ist. 7. Arrangement according to claim 6, wherein the low-pass filter is provided as an inductor is coil-like formation of the electrically conductive connection. 8. Anordnung nach Anspruch 6, bei der das Tiefpass-Filter durch eine Anordnung von Leiterbahnen in einem so geringen Abstand zueinander gebildet ist, dass ein Übersprechen zwischen diesen Leiterbahnen eine Filterwirkung für hohe Frequenzen bewirkt. 8. Arrangement according to claim 6, wherein the low pass filter through an arrangement of conductor tracks in such a small distance from one another that a Crosstalk between these traces has a filter effect for high frequencies. 9. Anordnung nach einem der Ansprüche 6 bis 8, bei der das Tiefpass-Filter in einer Metallschicht (7) auf einer Oberseite des Chipträgers (2) ausgebildet ist. 9. Arrangement according to one of claims 6 to 8, wherein the low-pass filter is formed in a metal layer ( 7 ) on an upper side of the chip carrier ( 2 ). 10. Anordnung nach Anspruch 9, bei der das Tiefpass-Filter in einer Metallschicht (7) ausgebildet ist, die auf einer Oberseite des Chipträgers aufgebracht ist, auf der der Halbleiterchip angebracht ist. 10. The arrangement according to claim 9, wherein the low-pass filter is formed in a metal layer ( 7 ) which is applied to an upper side of the chip carrier on which the semiconductor chip is attached. 11. Anordnung nach Anspruch 10, bei der der Halbleiterchip (1) so auf dem Chipträger angebracht ist, dass Anschlusskontakte des Halbleiterchips mit zugehörigen Anschlussflächen (14) der mit dem Tiefpass-Filter versehenen Metallschicht (7) verbunden sind. 11. The arrangement according to claim 10, wherein the semiconductor chip ( 1 ) is mounted on the chip carrier in such a way that connection contacts of the semiconductor chip are connected to associated connection surfaces ( 14 ) of the metal layer ( 7 ) provided with the low-pass filter. 12. Chipkarte mit einer Anordnung gemäß einem der Ansprüche 1 bis 11. 12. Chip card with an arrangement according to one of claims 1 until 11. 13. Chipmodul mit einer Anordnung gemäß einem der Ansprüche 1 bis 11, das für einen Einsatz in einer Smart-Card oder einer UICC vorgesehen ist. 13. Chip module with an arrangement according to one of claims 1 to 11 that for use in a smart card or a UICC is provided.
DE10142542A 2001-08-30 2001-08-30 Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier Withdrawn DE10142542A1 (en)

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DE10142542A DE10142542A1 (en) 2001-08-30 2001-08-30 Arrangement of semiconductor chip in chip carrier housing has conductive coating applied to semiconductor chip on opposite side to chip carrier
PCT/DE2002/003147 WO2003026006A2 (en) 2001-08-30 2002-08-28 Arrangement of a semiconductor in a housing, chip card and chip module

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005001934A2 (en) * 2003-06-30 2005-01-06 Siemens Aktiengesellschaft High-frequency package

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
DE19540647A1 (en) * 1995-04-14 1996-10-24 Mitsubishi Electric Corp Integrated semiconductor circuit device for central processing unit connected integrated circuit
DE19548046A1 (en) * 1995-12-21 1997-06-26 Siemens Matsushita Components Method for producing contacts of electrical components suitable for flip-chip assembly
DE19806818C1 (en) * 1998-02-18 1999-11-04 Siemens Matsushita Components Method for producing an electronic component, in particular an SAW component working with acoustic surface waves
EP1093159A1 (en) * 1999-10-15 2001-04-18 Thomson-Csf Method for encapsulating electronic components

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214691A (en) * 1990-01-18 1991-09-19 Fujitsu Ltd Integrated circuit mounting structure of flexible printed board
US5557142A (en) * 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5311059A (en) * 1992-01-24 1994-05-10 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
SE9600085D0 (en) * 1996-01-08 1996-01-08 Xicon Ab Shielding of electronic components that are baked directly on PCBs
EP1085572A3 (en) * 1999-09-16 2006-04-19 Texas Instruments Incorporated Low pass filter integral with semiconductor package
EP1098367A2 (en) * 1999-11-05 2001-05-09 Lucent Technologies Inc. An electronics package having an integrated filter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4717948A (en) * 1983-03-18 1988-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
DE19540647A1 (en) * 1995-04-14 1996-10-24 Mitsubishi Electric Corp Integrated semiconductor circuit device for central processing unit connected integrated circuit
DE19548046A1 (en) * 1995-12-21 1997-06-26 Siemens Matsushita Components Method for producing contacts of electrical components suitable for flip-chip assembly
DE19806818C1 (en) * 1998-02-18 1999-11-04 Siemens Matsushita Components Method for producing an electronic component, in particular an SAW component working with acoustic surface waves
EP1093159A1 (en) * 1999-10-15 2001-04-18 Thomson-Csf Method for encapsulating electronic components

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005001934A2 (en) * 2003-06-30 2005-01-06 Siemens Aktiengesellschaft High-frequency package
WO2005001934A3 (en) * 2003-06-30 2005-05-12 Siemens Ag High-frequency package

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