EP3381052A1 - Electrical component with thin solder resist layer and method for the production thereof - Google Patents
Electrical component with thin solder resist layer and method for the production thereofInfo
- Publication number
- EP3381052A1 EP3381052A1 EP16762778.5A EP16762778A EP3381052A1 EP 3381052 A1 EP3381052 A1 EP 3381052A1 EP 16762778 A EP16762778 A EP 16762778A EP 3381052 A1 EP3381052 A1 EP 3381052A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- carrier
- stop layer
- contact surface
- lss
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 39
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000004922 lacquer Substances 0.000 claims description 9
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- 239000003973 paint Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims 1
- 238000005538 encapsulation Methods 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract 1
- 239000000306 component Substances 0.000 description 81
- 239000010410 layer Substances 0.000 description 62
- 239000011241 protective layer Substances 0.000 description 8
- 238000001465 metallisation Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002075 main ingredient Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010948 rhodium Substances 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000010897 surface acoustic wave method Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/1605—Shape
- H01L2224/16057—Shape in side view
- H01L2224/16059—Shape in side view comprising protrusions or indentations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
Definitions
- SMT Surface Mounted Technology
- solderable bumps are used for electrical interconnection and mechanical connection between a carrier, e.g. B. a circuit board, and an electrical component, for. B. discrete components or modules used.
- the material of the bumps is in one step, z.
- solder paste may contain flux that attack the surface of the carrier when heated. Furthermore, there is a risk that solder paste gets to solderable surfaces that should remain free of solder, z. B. to avoid electrical short circuits.
- a protective layer eg. B. a solder stop layer, are covered.
- solder stop layer The problem with the use of a solder stop layer is the increased complexity in the manufacture of the components, since the solder stop layer must be structured so that in an optimal case, all sensitive areas, but not actually to be provided with Lot areas are covered by the protective layer. It also holds that electrical Components should have ever smaller dimensions. Conventional solder-stop layers are already so thick compared to current dimensions of bump connections that further problems can occur in further steps to encapsulate the devices. Many components are encapsulated and mechanically stabilized by pouring a mold over the top and then hardening the mass. The problem now is that the mold mass no longer sufficiently filled gaps between the component and the carrier when the gap is too low due to the thickness of the solder stop layer.
- a protective layer should there ⁇ at a good adhesion on the surface of the carrier aufwei ⁇ sen, high temperatures, eg. B. greater than 250 ° C in a reflow process, without enduring degradation, be mechanically stable, chemically neutral and passive and do not conduct the electric current.
- the protective layer should be as thin as possible.
- the electrical component comprises a carrier having an upper side, a metallized contact surface on the upper side and a solder stop layer covering a part of the upper side, but not the contact surface.
- the solder stop layer has a thickness of 200 nm or less.
- solder-stop layer has a thickness which Kgs ⁇ NEN even at the currently small dimensions of bump connections, thus gaps are still reliably filled small distances between the carrier and electrical component.
- the carrier can be a printed circuit board or a chip.
- the metallized contact surface is preferably a solderable metallized surface which is intended to be over a
- the metallized Kon ⁇ clock face may in particular be a so-called under- bump metallization, and in turn have a multilayer structure.
- solder-stop layer has a thickness Zvi ⁇ rule 30 nm and 80 nm.
- the device has a bump ball on the metallized contact surface.
- the bump ball on the metallized contact surface may then consist of a solder material that has been applied to the area of the metallized contact area by a stencil printing method. In a subsequent heating, the material melts and forms due to the Oberflä ⁇ chenschreib to form a relatively small surface, a ball.
- the metallized contact surface can with a further metallization on the top of the carrier, z. B. a signal line in the form of a stripline connected.
- a further metallization can be arranged on the upper side of the carrier.
- the two further metallizations next to the contact surface on the upper side of the carrier are covered by the solder stop layer.
- the solder stop layer may have poor solder wettability. Then, when heated, solder material automatically centers away from the region of poor wettability toward the metallized contact surface which is free of the material of the solder stop layer.
- the solder material and / or flux thereby engage emp ⁇ -sensitive areas on the upper side of the support not. Even if electrically conductive solder material remains on a Be ⁇ rich next to the contact surface, the solder stop layer acts as an electrical insulator and signal lines are not short-circuited.
- the component additionally comprises an electrical component.
- the electrical component may have a contact surface at the bottom.
- the Bauele ⁇ ment then further comprises a bump connection that connects the two contact surfaces.
- the carrier may have a plurality of further metallized contact surfaces on its surface.
- the device may also have a variety of different electrical components, which are connected and interconnected via bump connections with the metallized contact surfaces of the carrier, wherein each of the electrical compo ⁇ nents in turn have metallized contact surfaces on their lower sides.
- the electrical component or the electrical plurality ⁇ shear components may also each have a solder-stop layer on their undersides.
- the solder-stop layers of the electrical components can be conventional protective layers. They may also be solder stop layers of the type of protective layer present.
- the component when two protective layers are arranged between a component and the carrier, the advantage of the small thicknesses of the present protective layers comes into play, since the effect on the height of the free gap doubles. Accordingly, it is possible for the component to comprise a molding compound which covers at least parts of the top side of the carrier and at least one electrical component.
- the mold mass also fills the intermediate space between the electrical component and the carrier or between all electrical components and the carrier.
- a hermetically sealed volume between the component and the carrier remains free of the material of the mold mass.
- an additional frame structure can be arranged between the component and the carrier, which surrounds the cavity since ⁇ Lich. The cavity is then formed by the surfaces of the carrier and the component and by the frame.
- the component prefferably has a first signal line connected to the contact surface on the upper side of the contact surface
- Carrier comprises.
- the device further has a second Sig ⁇ naltechnisch at the top of the carrier.
- Both signal lines are at least partially be ⁇ covered by the solder-stop layer.
- the electrical resistance between the two signal lines is 100 ⁇ or more.
- the lateral distance between the signal lines can be of the order of 180 ym.
- the solder-stop layer has a thickness, which - is selected such that a minimum resistance of 100 ⁇ réellege ⁇ represents is - depending on the material of the layer.
- solder stop layer is silicon as
- Main component comprises or consists entirely of silicon.
- solder-stop layers of silicon or other material with similar electrical isolation properties can be made surprisingly easily using the method described below.
- all materials for the solder stop layer can be used that sufficiently provides a reasonable ⁇ accordingly low wettability by solder and a have low electrical conductivity. Is preferred that the materials with the usual Swisssme ⁇ methods such. As the semiconductor industry, can be deposited and adhere well to the top of the carrier.
- the solder stop layer can also include germanium as a main ingredient ⁇ part or consist of germanium.
- the solder stop layer can in principle consist of all dielectric materials. However, preference is given to those which can be deposited relatively easily as a correspondingly thin layer. These include in particular the materials that can be applied to surfaces in reactive or non-reactive PVD processes, for. For example, oxides and nitrides of silicon, titanium, aluminum or chromium.
- the component may have component structures on the upper side of the carrier or on the underside of at least one electrical component.
- the device structures may have a height of 40 ym or more.
- the component structures may be SAW component structures, BAW component structures, MEMS (micro-electro-mechanical system) device structures or GBAW devices.
- similar component ⁇ structures be.
- the carrier has on its upper side or the electrical component on its underside a com ⁇ plex topology, which are poor or not covered by conventional solder stop layers.
- the other solderable metal surfaces to be protected by the solder stop layer may be nickel, copper, Alloys of these two elements or alloys with these two elements, gold, silver, palladium, rhodium, tin, and / or zinc have.
- the number of contact surfaces, the electrical components and the contact surfaces of the electrical components is not limited in principle, especially in electrical components with integrated circuits, the electrical component and the carrier can be interconnected and connected over many hundreds of bump connections.
- the carrier is not limited to printed circuit boards.
- the carrier itself can an electrical component, which is arranged on ei ⁇ nem further carrier or a further electrical component, etc., and connected to be.
- a method for producing such an electrical component comprises the steps of: providing a carrier with an upper side and a metallized contact surface on the upper side,
- the lacquer layer may comprise a conventional material for photolithography processes and z. B. be applied by spin coating. After application of the material of the solder stop layer on the remaining portions of the structured varnish layer and on the vacant surfaces of the carrier, the material of the photoresist can be removed by stripping ⁇ ent. As a result, the structured solder stop layer in the form of the desired solder stop mask is produced without additional structuring of the material of the solder stop layer. This method reduces the complexity of the overall ⁇ process and the cost of manufacturing the device when compared with conventional methods.
- solder stop layer It is possible for the solder stop layer to have a thickness that is 200 nm or less.
- solder stop layer it is possible for the solder stop layer to have a thickness which is between 20 nm and 80 nm. It is possible that the formed during the process
- Lot stop layer comprises silicon or germanium as the main constituent ⁇ part or is completely made of silicon or germanium be ⁇ .
- Other materials with similar electrical properties and similar wettability are also possible.
- the electrical component has another solderable metal surface on the upper side and the solder stop layer is deposited directly onto the further solderable metal surface.
- the more solderable metal surface can be a metal surface ⁇ a signal line or a realized at the top of the carrier capacitive, inductive or re- sistiven element.
- the method comprises the steps
- Arranging solder paste at least on the contact surface, arranging an electrical component with a contact surface on its underside on the upper side of the carrier, reflowing the component and connecting the two contact surfaces by means of a bump connection,
- the method comprises the step of enveloping the electrical component with a mold mass.
- the mold mass also fills the area between the component and the carrier.
- the lacquer which is patterned prior to the application of the material of the solder-stop layer to form the solder-stop mask to preserver ⁇ th may ⁇ a thickness between 0.5 and 10 ⁇ , z. B. between ⁇ 2 ym and 4 ym, and have a standard paint semiconductor manufacturing be.
- the paint can be sprayed next to the spin on the top of the carrier who ⁇ .
- Fig. 1 a cross section through an electrical compo ⁇ ment
- Fig. 2 a cross section through a device with further
- FIG. 3 shows a cross section through a component with a
- Fig. 7 a fourth intermediate step
- Fig. 8 a first intermediate result in the production of egg ⁇ nes complex electrical component
- FIG. 9 shows a further intermediate step
- FIG. 10 shows a further intermediate step after heating
- FIG. 11 shows a cross section through a simple execution ⁇ form of the device
- Fig. 12 shows a cross section through an alternative exporting ⁇ approximate shape
- Fig. 13 shows a cross section through a component with a thin
- Lot stop layer and a mold mass that fills the gaps between the electrical component and the carrier are listed.
- FIG. 1 shows a cross section through a simple Ausure ⁇ tion form of the electrical component EB.
- the electrical component EB has a carrier TR, on which a metallized contact surface MK is structured.
- the metallized contact surface ⁇ MK is intended to be connected via a bump connection to an electrical component.
- a solder stop layer LSS is arranged on ⁇ which covers those areas of the top of the carrier TR, which should not come into direct contact with solder material.
- the metallized contact surface may be a so-called under-bump metallization UBM and have a good wettable surface.
- Figure 2 shows a cross section through a shape of a
- solder stop layer LSS reliably protects sensitive areas on the top side of the carrier TR against wetting with solder, if the top side of the carrier TR is sufficiently flat. If the component is to be encapsulated by a mold mass MM, provides a thick solder-stop layer LSS of all ⁇ recently an obstacle, that the filling of the gap Z between the bottom of the electrical component EK, the via bump connections BU connected to the carrier TR and is connected, and the carrier TR fills.
- Figure 3 shows a cross section through an electric element construction, in which a bump ball BU has already formed on the con tact surface ⁇ MK. Due to the surface tension of the solder, a ball-like structure at the pres ⁇ fen a reflow process formed. Compared with the height of the bump ball or the subsequent bump connection to an electrical component, the thickness of the solder stop layer LSS is very small.
- solderable surface LO On the surface of the support is a material with solderable surface LO, z. B. a signal line SL, which may include nickel, Kup ⁇ fer, gold or silver arranged.
- solder stop layer LSS there is a risk that the material of the bump ball BU does not collect on the contact surface MK, but attacks the signal conductor and optionally short-circuits the Sig ⁇ nalleiter and another circuit element at the top of the carrier.
- Figure 4 shows a cross section through a first stinkpro ⁇ domestic product in the production of the electrical component.
- the contact surface MK and the signal conductor SL are arranged as an example of elements to be protected on the upper side of the carrier TR.
- FIG. 5 shows a cross section through a further intermediate step, in which the entire surface, including the regions to be protected and the regions to be wetted later by the solder, are covered by a photoresist FL.
- FIG. 6 shows a cross section through a further intermediate step, in which the photoresist FL has been structured in such a way that that only the areas of MK, which should remain the material of the solder-stop layer later released, remain covered by the material of the photo ⁇ lacks FL. For this it is possible to selectively expose and develop the photoresist.
- FIG. 7 shows the result of a further intermediate step, in which the entire upper side of the previous electrical component is covered by the material of the later solder stop layer LSS.
- the sensitive areas are directly covered by the material of the solder stop layer LSS.
- solder is to be arranged later, is the ver ⁇ remaining residue of the photoresist FL between the material of the solder-stop layer LSS and the contact surface.
- Figure 8 shows the result of a further Ver ⁇ drive step in which the remaining radicals of the photo ⁇ lacks FL were removed along with the deposited thereon segments of the material of the solder-stop layer LSS so that the surface to be wetted without coverage by the Lot - Stop layer exposed.
- FIG. 9 shows the result of a further step, namely of applying a solder paste on LP regions corresponding in Wesent ⁇ union areas of the contact surfaces MK. Due to the precisely definable edges of the solder stop layer LSS, the lateral positioning accuracy when applying the solder paste LP need not be too high as long as a substantial area of the contact surface MK is covered by the solder paste LP.
- FIG. 10 shows the result of a further intermediate step in the production of the electrical component, in which the material of the solder paste LP after heating has concentrated to form a sphere at the location of the contact surface MK.
- Figure 11 shows a cross section through an electrical construction ⁇ element, in which the contact surface MK on the underside of the electrical component EK and the contact surface MK at the top of the carrier TR via a bump connection, which emerged from the bump ball of Figure 10 is connected.
- Figure 12 shows a cross section through a further exemplary embodiment in which the electrical component and the EK Trä ⁇ ger TR are connected via a plurality of bump connections BU and connected.
- a solder stop layer LSS which is preferably also thin, may be arranged on the underside of the electrical component EK.
- FIG. 13 shows a cross section through an encapsulated electrical component in which a molding compound MM envelopes the electrical component EK at the top side of the carrier TR and fills the gaps Z between the electrical component EK and the carrier TR.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102015120647.1A DE102015120647B4 (en) | 2015-11-27 | 2015-11-27 | Electrical device with thin solder stop layer and method of manufacture |
PCT/EP2016/070973 WO2017088998A1 (en) | 2015-11-27 | 2016-09-06 | Electrical component with thin solder resist layer and method for the production thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
EP3381052A1 true EP3381052A1 (en) | 2018-10-03 |
Family
ID=56883787
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP16762778.5A Withdrawn EP3381052A1 (en) | 2015-11-27 | 2016-09-06 | Electrical component with thin solder resist layer and method for the production thereof |
Country Status (8)
Country | Link |
---|---|
US (1) | US20180331062A1 (en) |
EP (1) | EP3381052A1 (en) |
JP (1) | JP2018536994A (en) |
KR (1) | KR20180088798A (en) |
CN (1) | CN108369935A (en) |
BR (1) | BR112018010666A8 (en) |
DE (1) | DE102015120647B4 (en) |
WO (1) | WO2017088998A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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FI130166B (en) | 2019-03-08 | 2023-03-23 | Picosun Oy | Solder mask |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03218644A (en) * | 1990-01-24 | 1991-09-26 | Sharp Corp | Connection structure of circuit board |
US5620131A (en) * | 1995-06-15 | 1997-04-15 | Lucent Technologies Inc. | Method of solder bonding |
US6294840B1 (en) * | 1999-11-18 | 2001-09-25 | Lsi Logic Corporation | Dual-thickness solder mask in integrated circuit package |
US6645791B2 (en) * | 2001-04-23 | 2003-11-11 | Fairchild Semiconductor | Semiconductor die package including carrier with mask |
US20050173803A1 (en) * | 2002-09-20 | 2005-08-11 | Victor Lu | Interlayer adhesion promoter for low k materials |
JP2006511938A (en) * | 2002-12-20 | 2006-04-06 | アギア システムズ インコーポレーテッド | Structure and method for bonding to copper interconnect structures |
US6790759B1 (en) * | 2003-07-31 | 2004-09-14 | Freescale Semiconductor, Inc. | Semiconductor device with strain relieving bump design |
US7294451B2 (en) * | 2003-11-18 | 2007-11-13 | Texas Instruments Incorporated | Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board |
US7132303B2 (en) * | 2003-12-18 | 2006-11-07 | Freescale Semiconductor, Inc. | Stacked semiconductor device assembly and method for forming |
KR100626617B1 (en) * | 2004-12-07 | 2006-09-25 | 삼성전자주식회사 | Ball land structure of circuit substrate for semiconductor package |
JP4795112B2 (en) * | 2006-05-17 | 2011-10-19 | 株式会社フジクラ | Manufacturing method of bonding substrate |
JP5031403B2 (en) * | 2007-03-01 | 2012-09-19 | 京セラケミカル株式会社 | Epoxy resin composition for sealing, resin-encapsulated semiconductor device and manufacturing method thereof |
US7812460B2 (en) * | 2008-05-30 | 2010-10-12 | Unimicron Technology Corp. | Packaging substrate and method for fabricating the same |
US9524945B2 (en) * | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
US8922004B2 (en) * | 2010-06-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump structures having sidewall protection layers |
TWI575684B (en) * | 2011-06-13 | 2017-03-21 | 矽品精密工業股份有限公司 | Chip-scale package structure |
KR101307436B1 (en) * | 2011-11-10 | 2013-09-12 | (주)유우일렉트로닉스 | Mems sensor pakiging and the method |
US10192804B2 (en) * | 2012-07-09 | 2019-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace packaging structure and method for forming the same |
GB2520952A (en) * | 2013-12-04 | 2015-06-10 | Ibm | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
CN104637967A (en) * | 2015-02-13 | 2015-05-20 | 苏州晶方半导体科技股份有限公司 | Packaging method and packaging structure |
US9859234B2 (en) * | 2015-08-06 | 2018-01-02 | Invensas Corporation | Methods and structures to repair device warpage |
-
2015
- 2015-11-27 DE DE102015120647.1A patent/DE102015120647B4/en active Active
-
2016
- 2016-09-06 BR BR112018010666A patent/BR112018010666A8/en not_active Application Discontinuation
- 2016-09-06 US US15/776,019 patent/US20180331062A1/en not_active Abandoned
- 2016-09-06 EP EP16762778.5A patent/EP3381052A1/en not_active Withdrawn
- 2016-09-06 CN CN201680062169.7A patent/CN108369935A/en active Pending
- 2016-09-06 JP JP2018527165A patent/JP2018536994A/en not_active Ceased
- 2016-09-06 WO PCT/EP2016/070973 patent/WO2017088998A1/en active Application Filing
- 2016-09-06 KR KR1020187011776A patent/KR20180088798A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
DE102015120647B4 (en) | 2017-12-28 |
CN108369935A (en) | 2018-08-03 |
WO2017088998A1 (en) | 2017-06-01 |
US20180331062A1 (en) | 2018-11-15 |
KR20180088798A (en) | 2018-08-07 |
BR112018010666A2 (en) | 2018-11-13 |
JP2018536994A (en) | 2018-12-13 |
DE102015120647A1 (en) | 2017-06-01 |
BR112018010666A8 (en) | 2019-02-26 |
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