EP0733961B1 - Referenzstromgenerator in CMOS-Technologie - Google Patents

Referenzstromgenerator in CMOS-Technologie Download PDF

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Publication number
EP0733961B1
EP0733961B1 EP96400595A EP96400595A EP0733961B1 EP 0733961 B1 EP0733961 B1 EP 0733961B1 EP 96400595 A EP96400595 A EP 96400595A EP 96400595 A EP96400595 A EP 96400595A EP 0733961 B1 EP0733961 B1 EP 0733961B1
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EP
European Patent Office
Prior art keywords
transistor
transistors
reference current
current generator
branch
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Expired - Lifetime
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EP96400595A
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English (en)
French (fr)
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EP0733961A1 (de
Inventor
Henri Oguey
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Centre Suisse dElectronique et Microtechnique SA CSEM
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Centre Suisse dElectronique et Microtechnique SA CSEM
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage

Definitions

  • the present invention relates to generators of reference current realized in CMOS technology.
  • Figure 1 of the accompanying drawings shows an example of such a reference current generator produced according to the prior art. You can find a description in an article by E. Vittoz and J. Felrath, published in the IEEE review, Journal of Solid State Circuits, Vol. SC-12, pp. 224-231, June 1977, and entitled "CMOS analog integrated circuits based on weak inversion operation " integrated analog based on low operation inversion).
  • This known generator comprises two P channel transistors, MPA and MPB forming a current mirror, two MNA and MNB transistors which are regulation transistors and a resistor R which forms the element on which the current reference is based.
  • the whole of this assembly is connected between the supply voltages V DD and V SS , the reference current being able to be taken from the supply terminal V DD , for example.
  • the regulation transistors operate at low inversion, which means that their gate voltage Vg is less than their threshold voltage V T and that the drain current I D decreases exponentially with the source voltage V S , according to the formula: where I DO is a parameter which depends on the grid-substrate voltage, W and L are respectively the length and the width of the channel and U T is a voltage proportional to the absolute temperature, being worth approximately 26 mV at ambient temperature.
  • I DO is a parameter which depends on the grid-substrate voltage
  • W and L are respectively the length and the width of the channel
  • U T is a voltage proportional to the absolute temperature, being worth approximately 26 mV at ambient temperature.
  • CMOS circuit designers being general to create components with size and consumption as low as possible, the presence of a resistance in a circuit is often considered a significant drawback. Indeed, especially if the current at supply is low, resistance of high value is required, this which requires an excessive silicon surface, if the resistivity (resistance per square) of the layer serving as resistance is low.
  • document EP 0 454 150 already proposes a reference current generator made in CMOS technology and free of resistance.
  • This generator includes a first current mirror which forms two branches of circuit intended for be connected between polarity supply terminals opposite and each comprising a group of transistors connected in series and of opposite conductivity types.
  • a first of the branches includes, put in series with its transistors, a stabilization transistor forming a variable conductance to impose on the transistor which is there connected in this first branch a source voltage predetermined.
  • a second mirror is provided. current which forms a third branch of the assembly.
  • the third branch comprises the series connection of two transistors with one end is connected to the gate of the stabilization transistor and whose the other end is connected to the node between it transistor and the first branch.
  • control voltage applied to the gate of the stabilization transistor is equal to the sum of gate-source voltages of the third branch transistors, which corresponds to a value greater than twice the voltage threshold of these transistors.
  • This control voltage is not stable only if the third branch transistors and the transistor of the same type of conductivity of the second branch are arranged in separate boxes, which is a severe technological constraint.
  • Another drawback is that the circuit is very sensitive to the threshold voltages of the transistors, because the reference current obtained is a function of threshold voltages transistors of the third branch of the assembly. Moreover, he requires relatively high supply voltage greater than the sum of the aforementioned threshold voltages of these third branch transistors.
  • the object of the invention is to propose a generator for reference voltage devoid of these drawbacks.
  • the subject of the invention is therefore a generator of reference made in CMOS technology including a first current mirror which forms two branches of circuit intended for be connected between polarity supply terminals opposite and each comprising a group of transistors connected in series and of opposite conductivity types, a first of said circuit branches comprising, put in series with its transistors, a stabilization transistor forming a variable conductance to impose on the transistor which is there connected in this first circuit branch a source voltage predetermined, this reference current generator comprising also a second current mirror which includes a third circuit branch, and being characterized in that said second current mirror is connected to generate in said third circuit branch an image of the current circulating in said first circuit branch, said third circuit branch being connected to at least one said supply terminals, said third circuit branch comprising, connected in series, two transistors, respectively of opposite conductivity types and on the common node of which is taken a control voltage applied to the grid of said stabilization transistor.
  • the generator according to the invention consists exclusively of active components which can be easily integrated with good reproducibility and which take up little space on the integrated circuit chip.
  • Figure 2 shows a block diagram of the embodiment preferred of the invention.
  • the sources of two channel P transistors, respectively MP1 and MP2 are connected to a supply line V DD and their gates are connected to each other to form a node 1.
  • the drains of these transistors are respectively connected to the drains of two N channel transistors, MN1 and MN2.
  • the connection between the drain of transistor MP1 and the transistor MN1 is also connected to node 1.
  • the gates of the transistors MN1 and MN2 are also connected together and form a node 2 to which is connected also the drain of transistor MN2.
  • MN3 and MN4 are connected by their sources to a supply line V SS , their gates being connected to each other to form a node 3 to which the drain of transistor MN3 is also connected.
  • the transistor MN4 is an active component operating as a controlled conductance.
  • the source of transistor MN1 is connected to the drain of transistor MN4 thus forming a node 4, and that of transistor MN2 is connected to the supply line V SS .
  • the drain of transistor MN3 is connected to the drain of a channel P transistor, MP3, the source of which is connected to the supply line V DD and the gate of which is connected to node 1.
  • the transistors MN1 and MN2 of this circuit operate at low inversion, which means that their gate voltage is lower than their threshold voltage V T and that the drain current I D is a decreasing exponential function of the source voltage V S , according to formula (1). Furthermore, the transistors MN3 and MN4 work in strong inversion, in other words their gate voltage is greater than their threshold voltage V T. Finally, the voltage V DD is chosen to be high enough so that, except for the transistor MN4, all the transistors are in saturation.
  • U T kT / q is the thermodynamic tension, proportional to the absolute temperature T, and is worth approximately 26 mV at room temperature.
  • Vg n3 2 i 3 ⁇ not 3 + V Tn
  • FIG. 6 shows the shape of this current i ' 1 , the graph showing on the abscissa the current i 1 imposed by the current mirror and on the ordinate the theoretical currents determined according to the above equations.
  • the current i R is a stable parameter of the circuit so that it constitutes a current reference. It will be noted that this current is only determined by the dimensioning of the transistors, in other words by the topography of the circuit which can be reproduced with precision from one circuit to another.
  • the current reference can be taken from the supply terminal V DD , the current serving as a reference then being formed by the sum of the currents i 1 (i R ), i 2 and i 3 .
  • the circuit of figure 3 takes again the diagram of the Figure 2 so that we find the same transistors connected the same way. She shows three other ways to generate a reference current.
  • the first consists in using an additional channel transistor P, MP4, the gate of which is connected to node 1. Its source is connected to terminal V DD , while the reference current i 4 can be taken from the drain of this transistor.
  • the second possibility consists in using an N channel transistor, MN5, the gate of which is connected to the drain of transistor MN3, the source of which is connected to terminal V SS of the circuit and the drain of which will receive the reference current i 5 .
  • the third possibility consists in also using an N channel transistor, MN6, the gate of which is connected to node 2 and which, moreover, is connected in the same way as the transistor MN5. It will be supplied with the reference current i 6 .
  • the transistors MP4, MN5 and MN6 To provide currents close to the desired reference currents, they must be in saturation, that is to say that their drain-source voltage must, in absolute value, be greater than a limit Vd sat .
  • MN5 and MN6 do not load the nodes to which they are connected, we can multiply the number and thus provide reference currents at many points in a circuit most important which the current generator can do part.
  • FIG. 4 shows more particularly an example of a starting circuit for the reference current generator according to the invention. Indeed, such a circuit is necessary to avoid that the generator remains initially blocked.
  • the starting circuit comprises an N channel transistor, MN7, the source of which is connected to the terminal V SS and the drain of which is connected to node 1.
  • the circuit further comprises a second N channel transistor, MN8 of which the gate is connected to node 2, the source of which is connected to the terminal V SS and the drain of which is connected both to the gate of the transistor MN7 and to a capacitor C which is also connected to the terminal V DD .
  • the capacitor C is discharged at startup which makes drive transistor MN7 and circulate an initial current in transistors MP1 to MP3.
  • the transistor MN8 charges capacitor C, which blocks transistor MN7. The generator then operates at normal speed.
  • Figure 5 schematically shows a way advantageous to produce the generator according to the invention. This diagram includes both the transistors to generate a reference current and those for starting the circuit.
  • the transistors are advantageous to distribute according to the nature of their operating conditions. So, belong to preference to a first group MP all channel transistors P with strong inversion, to a second group MNA the transistors N channel with low inversion, while a third group includes high inversion N channel transistors.
  • the transistor MN1 in Figure 2 can actually be formed by six unitary transistors arranged in parallel
  • i 1 20nA
  • i 2 20nA
  • i 3 60nA
  • i 4 40nA
  • i 5 120nA.
  • all the transistors in each group can be identical and have for example the following dimensions: MP group MNA Group MNB Group W 6 50 6 L 50 6 207 i / ⁇ 6.6710 -3 3.710 -5 3.10 -2 ⁇ 2.88 542 1.88
  • the generator according to the invention is well suited to supply reference currents of less than 1 ⁇ A. Its size is reduced, while its own consumption can be of the order of 5i 1 only.
  • FIGS 7, 8 and 9 show three variants of the reference current generator according to the invention.
  • the transistors in saturation can, for a given gate voltage and especially if the length of their channel is small, present a slight variation in drain current depending on the drain voltage.
  • the reference current can undergo a certain dependence on the supply voltage (a few% per Volt). In the circuit shown, these are especially the transistors MN1 and MN2 which are responsible for this effect.
  • auxiliary transistors MN11 and MN12 are respectively inserted in series with the transistors MN1 and MN2.
  • the gates of these transistors are connected in common to the junction between the transistor MN12 and the transistor MP2. It follows that the drain voltages of the transistors MN1 and MN2 are substantially equal and independent of variations in the voltage V DD .
  • FIG. 8 shows a variant offering the possibility of adjusting the reference current from outside the circuit.
  • the MP3 transistor is broken down into several unitary transistors MP3a, MP3b, MP3c .... which are respectively connected in series with as many switching transistors P channel Sa, Sb, Sc
  • the gate of the first transistor Sa is directly connected to terminal V SS . He is therefore a driver at all times.
  • the gates of the other transistors Sb Sc .... are connected to a logic control circuit CL making it possible to make these transistors selectively conductive.
  • the effective width of the MP3 transistor that is to say its parameter K 2 (equation 15) can be adjusted from the outside.
  • This circuit is especially desirable if, during manufacture, the current dispersion from one batch of circuits to another is significant.
  • Figure 9 shows a third variant of the generator according to the invention in which, all things equal by considering Figure 2, the source of the transistor MN3 is connected to the drain of a transistor MN4 ' and at the source of transistor MN1.
  • the transistor MN4 ' is therefore traversed by the sum of the currents i 1 and i 3 .
  • the transistor MN4 'so that it has the same drain voltage as the transistor MN4, but for a current i 1 + i 3 instead of i 1 , therefore K 2 +1 times greater.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Claims (13)

  1. Referenzstromgenerator in CMOS-Technologie, mit einem ersten Stromspiegel, der zwei Schaltungszweige bildet, die zwischen Versorgungsanschlüsse (VDD, VSS) entgegengesetzter Polarität zu schalten sind und die jeweils eine Gruppe von Transistoren (MP1, MN1; MP2, MN2) enthalten, welche in Reihe geschaltet und von entgegengesetztem Leitfähigkeitstyp sind, wobei ein erster der Schaltungszweige einen mit seinen Transistoren in Reihe geschalteten Stabilisierungstransistor (MN4, MN4') aufweist, der eine veränderliche Konduktanz bildet, um dem Transistor (MN1), der mit ihm in dem ersten Schaltungszweig verbunden ist, eine vorgegebene Sourcespannung (Vsn1) aufzuprägen, wobei der Referenzstromgenerator ferner einen zweiten Stromspiegel (MP1, MP3) enthält, der einen dritten Schaltungszweig aufweist, dadurch gekennzeichnet, daß der zweite Stromspiegel so geschaltet ist, daß er in dem dritten Schaltungszweig ein Bild (i3) des im ersten Schaltungszweig fließenden Stromes (i1) erzeugt, der dritte Schaltungszweig mit mindestens einem der Versorgungsanschlüsse (VDD) verbunden ist, der dritte Schaltungszweig zwei in Reihe geschalteteTransistoren (MP3, MN3) entgegengesetzten Leitfähigkeitstyps aufweist, an deren gemeinsamen Knoten eine Steuerspannung abgreifbar ist, die an das Gate (Vgn3) des Stabilisierungstransistors (MN4, MN4') angelegt wird.
  2. Referenzstromgenerator nach Anspruch 1, dadurch gekennzeichnet, daß der Stabilisierungstransistor (MN4, MN4') im Nicht-Sättigungsbereich und bei starker Inversion arbeitet.
  3. Referenzstromgenerator nach einem der Ansprüche 1 und 2, dadurch gekennzeichnet, daß der Transistor (MN3) des zweiten Stromspiegels, der vom gleichen Leitfähigkeitstyp wie der Stabilisierungstransistor MN4) ist, mit seinem Gate an dem besagten Knoten und mit seiner Source an einer Konstantpotentialquelle angeschlossen ist.
  4. Referenzstromgenerator nach Anspruch 3, dadurch gekennzeichnet, daß die Konstantpotentialquelle ein mit dem Stabilsierungstransistor (MN4') verbundener Knoten des ersten Zweiges ist.
  5. Referenzstromgenerator nach Anspruch 3, dadurch gekennzeichnet, daß die Konstantpotentialquelle derjenige Anschluß (VSS) unter den Versorgungsanschlüssen ist, der dem Stabilisierungstransistor (MN4) gemeinsam ist.
  6. Referenzstromgenerator nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß mit Ausnahme des Stabilisierungstransistors (MN4, MN4') sämtliche Transistoren im Sättigungsbereich arbeiten.
  7. Referenzstromgenerator nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, daß jeder der Zweige einen P-Kanal-Transistor (MP1 bzw.MP2 bzw. MP3) und mindestens einen N-Kanal-Transistor (MN1 bzw. MN2 bzw. MN3) enthält und daß der Stabilisierungstransistor ein N-Kanal-Transistor (MN4; MN4') ist.
  8. Referenzstromgenerator nach Anspruch 7, dadurch gekennzeichnet, daß der Transistor (MN4), der im Nicht-Sättigigungsbereich arbeitet, in den ersten Zweig in Reihe geschaltet ist.
  9. Referenzstromgenerator nach Anspruch 7, dadurch gekennzeichnet, daß der Transistor (MN4'), der im Nicht-Sättigungsbereich arbeitet, gleichzeitig in den ersten Zweig und in den dritten Zweig in Reihe geschaltet ist.
  10. Referenzstromgenerator nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet, daß er mindestens einen zusätzlichen Transistor (MP4, MN5, MN6) zum Abgreifen eines Referenzstromes (i4, i5,i6) aufweist, der so geschaltet ist, daß er durch die Spannung gesteuert wird, welche an dem Knoten (1 bzw. 2 bzw. 3) zwischen den Transistoren entgegengesetzten Leitfähigkeitstyps in einem entsprechenden Zweig anliegt.
  11. Referenzstromgenerator nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß der erste und zweite Zweig mindestens einen in Reihe geschalteten zusätzlichen Transistor (MN11, MN12) enthält.
  12. Referenzstromgenerator nach einem der Ansprüche 1 bis 11, dadurch gekennzeichnet, daß die Transistoren desselben Leitfähigkeitstyps und/oder Inversionstyps in getrennten Gruppen (MP, MNA, MNB) angeordnet sind und daß mindestens ein Transistor in jeder Gruppe von einer vorgegebenen Anzahl an Einzeltransistoren gebildet wird, die die gleichen Abmessungseigenschaften haben und gemeinsam den Transistor bilden.
  13. Referenzstromgenerator nach Anspruch 12, dadurch gekennzeichnet, daß die Unijunktionstransistoren mindestens einer der Transistorgruppen (MP) mit einem Schalttransistor (Sa, Sb, Sc) in Reihe geschaltet sind, der eine Auswahl des Einzeltransistors ermöglicht, und daß er ferner eine Logikschaltung (CL) aufweist, um eine wahlweise Steuerung der Schalttransistoren zu ermöglichen.
EP96400595A 1995-03-22 1996-03-21 Referenzstromgenerator in CMOS-Technologie Expired - Lifetime EP0733961B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9503352 1995-03-22
FR9503352A FR2732129B1 (fr) 1995-03-22 1995-03-22 Generateur de courant de reference en technologie cmos

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EP0733961A1 EP0733961A1 (de) 1996-09-25
EP0733961B1 true EP0733961B1 (de) 2000-07-05

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EP (1) EP0733961B1 (de)
DE (1) DE69609104T2 (de)
FR (1) FR2732129B1 (de)

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Publication number Publication date
FR2732129B1 (fr) 1997-06-20
FR2732129A1 (fr) 1996-09-27
DE69609104T2 (de) 2001-03-15
DE69609104D1 (de) 2000-08-10
EP0733961A1 (de) 1996-09-25
US5949278A (en) 1999-09-07

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