Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
  • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/0021—Modifications of threshold
  • H03K19/0027—Modifications of threshold in field effect transistor circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
  • H03F3/45273—Mirror types
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
  • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
  • H03F3/45488—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by using feedback means
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
  • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
  • H03K19/17736—Structural details of routing resources
  • H03K19/17744—Structural details of routing resources for input/output signals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
  • H03L7/097—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a comparator for comparing the voltages obtained from two frequency to voltage converters
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
  • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
  • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
  • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
  • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]

Definitions

• TITLE Physically non-clonable function device
• Modes of implementation and embodiment of the invention relate to physically non-clonable functions (PUF: Physical Unclonable Function), and in particular those performed within an integrated circuit.
• PEF Physical Unclonable Function
• a physically non-clonable function automatically generates a unique non-predictable code which depends on random or partially random physical characteristics of the physically non-clonable function. These physical characteristics can be caused by variations during the fabrication of the physically clonable function.
• the content of the generated code which is unique because it differs from a physically non-clonable function to another physically non-clonable function, cannot be expected and may depend, for example, on a particular configuration of components during the power up the function.
• a physically non-clonable function can be performed by a non-volatile memory which has a content upon power-up which depends on the partially random physical characteristics of the memory, these manufacturing variations leading to different physical characteristics for different memories.
• Physically non-clonable functions can be performed using, for example, live or non-volatile memories, or ring oscillators or specific logic circuits.
• the variability of the physically non-clonable function is due not only to the variability of the threshold voltages of the transistors but also to other parameters which are difficult to control, for example the formation of diodes resulting from connections between PMOS and NMOS transistors.
• an integrated device of physically non-clonable functions is proposed based on a set of MOS transistors mounted in diodes having a random distribution of threshold voltages resulting during the conventional process for manufacturing transistors, implantations of dopants leading to implanted source and drain regions with
• control transistors which will make it possible to define a reference current equal to or substantially equal to the average of the currents flowing in these control transistors.
• the other transistors will be used to define the digital output code of the function physically not clonable. All of these other transistors have, by their random distribution of threshold voltages, a random distribution of drain-source currents and the comparison of each drain-source current of a transistor associated with a bit of the digital code with said reference current, will allow to define the logical value 0 or 1 of this bit.
• a fixed gate voltage is imposed whatever the value of the source drain current passing through it.
• an integrated circuit comprising at least one domain comprising a physically non-clonable function device.
• Said device comprises a set of MOS transistors mounted in diodes having a random distribution of respective threshold voltages.
• This set includes N first transistors and at least one second transistor.
• the device also comprises at least one output node of said function capable of delivering a signal the level of which depends on the comparison between a first current obtained from a reference current equal to or substantially equal to the average of the currents flowing in the N first transistors, and a second current obtained from a current flowing in said at least one second transistor.
• the term "obtained" has a very broad meaning.
• a current obtained from another current can be equal to this other current or else different from this other current while being obtained from this other current, for example by algebraically adding an offset current to this other current.
• the addition of an offset current to the reference current and the addition of the same offset current to the current flowing in said at least one second transistor makes it possible to implement an embodiment making it possible to further reduce the effects of aging of the transistors, or even to overcome them.
• the group of N first transistors forms a group of “control” transistors which will make it possible to define said reference current.
• This reference current can be equal to the average of the currents flowing in the N first transistors or in some cases slightly different from this average, for example to identify risks of instability in said comparison when the current flowing in a second transistor is too close to the reference current equal to said average.
• the expression "equal to or substantially equal to said average” can be understood to mean “equal to said average except for a tolerance”. This tolerance can for example be equal to more or less a few tens of percent of said average.
• each second transistor will be associated with an output signal whose value will make it possible to define a logical value of a bit of a unique digital code delivered by the physically non-clonable function, for example during the energizing said domain of the integrated circuit.
• the number of second transistors is higher since it defines the number of bits of the code delivered by the function. And when this code is advantageously used as a key, it is preferable that this number of bits is large, at least greater than 10, for example 64 or 128.
• the number N is sufficiently large.
• N preferably greater than or equal to 10
• this number N possibly being much greater, for example of the order of 100, without this value being limiting.
• the number N of first transistors is equal to the number of second transistors.
• the device further comprises a first means configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current flowing in this first transistor, and a second means configured to impose on each second transistor a respective gate voltage fixed whatever the value of the current flowing in this second transistor.
• the first means comprises, for each first transistor, a first negative gain amplifier, the output of which is looped back via a first bias transistor on its input, which is also coupled to the gate of the first transistor.
• the first bias transistor is advantageously intended to bias the gate of the first transistor, and has a first conduction electrode, for example the source, coupled to said input and a second conduction electrode, for example the drain.
• bias transistors associated with the first N transistors are mutually connected.
• the first amplifier will, via the source gate voltage of the first bias transistor, bias the gate of the first transistor, and will stabilize the gate voltage of the first transistor at a fixed value regardless of the value of the current flowing in this first transistor, due to the negative gain loopback of the output terminal on its input.
• said first amplifier comprises a first input transistor, mounted as a common source, the gate of which is coupled to said input of the first amplifier, of which a first conduction electrode, for example the source, is connected to a reference supply terminal, for example the ground, and a second conduction electrode of which, for example the drain, is coupled to the output of the first amplifier which is itself, coupled to a first bias stage as well as to the gate of the first bias transistor.
• the common source mounting of the first input transistor makes it possible to obtain the negative gain.
• this transistor mounted as a common source will make it possible to better follow the variations in the manufacturing process and the temperature variations, and consequently to make the
• the first amplifier further comprises a cascode transistor connected between the second electrode of the first input transistor and the output of the first amplifier.
• This cascode transistor makes it possible to equalize the source drain voltage of the first input transistor with the source drain voltage of the first transistor, so as to place these two transistors in the same polarization state and in the same conduction regime.
• the first N transistors, the first amplifier and the first bias transistor are of the same type of conductivity, for example of the type of conductivity N.
• the second means comprises, for each second transistor, a second negative gain amplifier, the output of which is looped back via a second bias transistor on its input which is coupled to the gate of the second transistor.
• the second bias transistor is advantageously intended to bias the gate of the second transistor, and has a first conduction electrode, for example the source, coupled to said input and a second conduction electrode, for example the drain, coupled (directly or indirectly) to the output node
• said second amplifier comprises a second input transistor, mounted as a common source, the gate of which is coupled to said input of the second amplifier, of which a first conduction electrode is connected to a reference supply terminal and a second conduction electrode of which is coupled to the output of the second amplifier which is coupled to a second bias stage as well as to the gate of the second bias transistor.
• the second amplifier advantageously further comprises a cascode transistor connected between the second conduction electrode of the second input transistor and the output of the second amplifier.
• the second amplifier and the second bias transistor are of the same type of conductivity, for example of the type of conductivity N.
• the first means and the second means are structurally identical, and the transistors of the first means and the transistors of the second means are paired transistors.
• said first current can be the reference current and said second current is the current flowing in said at least one second transistor.
• the device further comprises between the first means and the second means, a current mirror stage configured to deliver said reference current from the sum of the currents flowing in the first transistors .
• the current mirror has a division ratio equal to 1 / N.
• the current mirror preferably has an adjustable division ratio between several values comprising the value 1 / N and auxiliary values situated on either side. other of the value 1 / N.
• said first current is said reference current algebraically increased by an offset current
• said second current is the current flowing in said at least one second transistor algebraically increased by said offset current
• algebraically increased by an offset current means “increased by an offset current” if this offset current is positive or “decreased by the absolute value of an offset current” if this offset current is negative.
• the device comprises
• each first branch comprises
• a second part incorporating a first additional transistor mounted as a diode.
• Said second part is common to all the first branches, and the first parts of all the first branches are connected to said second common part.
• each second branch incorporates the corresponding second transistor, the corresponding second means and a second additional transistor mounted as a diode.
• the first additional transistor and each second additional transistor are configured to have the same gate-source voltage and the same drain-source voltage.
• the device comprises
• a first additional current mirror incorporating said first additional transistor and configured to deliver, from the current flowing in said second common part, a first intermediate current equal to the average of the currents flowing in the N first transistors algebraically increased by the offset current , and
• the first additional mirror has a division ratio equal to 1 / N and incorporates another first additional transistor, the first two additional transistors being configured to have the same gate-source voltage but respective drain-source voltages different.
• Each second additional mirror has for example a division ratio equal to one and incorporates another second transistor additional, the two second additional transistors being configured to have the same gate-source voltage but different respective drain-source voltages.
• the other first additional transistor and each other second additional transistor advantageously have the same gate-source voltage and the same drain-source voltage.
• the device further comprises
• a first system of cascoded current mirrors coupled between on the one hand the first additional current mirror and on the other hand each output node and configured to deliver said first current from the first intermediate current
• the first system of cascoded current mirrors has a division ratio equal to one.
• the first system of cascoded current mirrors preferably has an adjustable division ratio between several values comprising the value one and auxiliary values located on the one hand and else of value one.
• a method for automatically generating a unique code that cannot be predicted at each output node of a physically non-clonable function device belonging to an integrated circuit as defined above, comprising at least one energizing the domain of the integrated circuit incorporating said device.
• the method comprises at least two additional energizations with respectively shifts of the reference current with respect to the average of currents flowing in the N first transistors, the shifts being carried out respectively on either side of said average.
• FIG. 1 schematically illustrates an embodiment of an integrated circuit according to the invention
• FIG. 2 schematically illustrates an embodiment of a physically non-clonable function device according to the invention
• FIG. 3 schematically illustrates a random distribution of threshold voltages of transistors of a function device
• FIG. 4 schematically illustrates another random distribution relating to a physically non-clonable function according to the invention
• FIG. 5 schematically illustrates a variant of the invention
• FIGS. 6 and 7 schematically illustrate other embodiments and implementation of the invention.
• the reference WF designates a semiconductor plate (or “wafer” in English) presenting in a conventional and known manner LDC cutting lines of the zones of the plate each containing an integrated circuit IC.
• This integrated circuit IC here contains a domain DD incorporating a device DIS of function which is not physically clonable.
• the substrate in and on which the various DIS devices are produced can be a solid substrate or else a substrate of the silicon on insulator type (SOI: Silicon On Insulator).
• SOI Silicon On Insulator
• FIG. 2 schematically illustrates a possible embodiment of a DIS device with a physically non-clonable function.
• This device DIS here comprises a set of MOS transistors, here for example NMOS transistors, TR1 i, TR2j having a random distribution of respective threshold voltage.
• This set of MOS transistors comprises a group of N first transistors TR1 1 -TR1N and in this example, K second transistors TR21 -TR2K which, as will be seen in more detail below, will make it possible to define the logical values of K bits a code generated at the output of the physically non-clonable function device DIS.
• the random distribution DB 1 of threshold voltage VT is illustrated very schematically in FIG. 3 and can be reflected in particular, as illustrated in FIG. 4, by a random distribution DB2 of the ratio Ion / Ioff between the current Ion from the transistor to the on state and the current Ioff of the transistor in the off state
• the values of the currents Ion of the various transistors TR1 i and TR2j vary around an average value of a few microamperes, for example between 1 and 10 microamperes, per micrometer with a deviation comprised for example between 15% and 50%.
• each first transistor TR1 i (i varying from 1 to N) is an NMOS transistor arranged in a diode arrangement, that is to say the gate of which is connected to the drain, for example by metallization.
• All the first transistors TR1 i are connected, by their source, to a reference supply voltage, for example the GND ground.
• the device DIS further comprises a first means FM 1 1 - FM 1N, configured to impose on each first transistor TR1 i a respective fixed gate voltage regardless of the value of the current flowing in this first transistor TRl i.
• this fixed gate voltage may not be identical for all the first transistors TR1 i.
• the first FM 1 1 means comprises a first amplifier TRE 1 with negative gain, the output BS of which is looped back via a first bias transistor TRPL 1 on its input BE.
• This input BE is coupled to the gate of the first transistor TRI 1.
• the first bias transistor TRPL1 is intended to bias the gate of the first transistor TRI 1.
• the first bias transistor TRPL 1 has a first conduction electrode, here the source S I, coupled to said input BE and a second conduction electrode, here the drain D l.
• the N second conduction electrodes D l of the N first polarization transistors respectively associated with the N first transistors TR1 i, i varying from 1 to N, are mutually connected.
• Said first amplifier comprises in this example, a first input transistor TRE 1, mounted as a common source, the gate of which is coupled to said input BE of the first amplifier.
• the first input transistor TRE 1 has a first conduction electrode, here the source S, connected to the reference supply terminal GND and a second conduction electrode, here the drain D, coupled to the output BS of the first amplifier via a cascode transistor TRC 1, the gate of which is connected to the supply voltage Vdd.
• This cascode transistor TRC which is not essential, makes it possible to equalize the source drain voltage of the first input transistor with the source drain voltage of the first transistor TR1 i, so as to place these two transistors in the same polarization state and in the same conduction regime.
• the output BS of the first amplifier is coupled to a first polarization stage POL I of conventional and known structure.
• the output BS is also coupled to the gate of the first bias transistor TRPL 1.
• the first N transistors, the first amplifier and the first bias transistor are of the same type of conductivity, here the type of conductivity N. In other words, all these transistors are NMOS transistors.
• the first amplifier having a negative gain, will, via the source gate voltage of the first bias transistor TRPL 1, bias the gate of the first transistor TR1 1, and will stabilize the gate voltage of the first transistor TRI 1 at a fixed value which let the value of the current flowing in this first transistor TR1 1 be due to the negative feedback of the output terminal on its input.
• Each second transistor TR2j (j varying from 1 to K) is an NMOS transistor arranged in a diode arrangement, that is to say the gate of which is connected to the drain, for example by metallization.
• All the second transistors TR2j are connected, by their source, to a reference supply voltage, for example the GND ground.
• the device DIS further comprises a second means SM2j, j varying from 1 to K, configured to impose on each second transistor TR2j a respective fixed gate voltage regardless of the value of the current flowing in this second transistor TR2j.
• this fixed gate voltage may not be identical for all the second transistors TR2j.
• the structure of the means SM2j and that of the means FM l i are identical and the transistors which compose them are matched, so as to have characteristics which vary identically following variations in temperature or following an aging phenomenon.
• the second means SM21 includes a second amplifier TRE2 with negative gain, the output BS of which is looped through a second bias transistor TRPL2 on its BE input.
• This BE input is coupled to the gate of the second transistor
• the second bias transistor TRPL2 is intended to bias the gate of the second transistor TR21.
• the second bias transistor TRPL2 has a first conduction electrode, here the source S2, coupled to said input BE and a second conduction electrode, here the drain D2.
• the second electrode D2 is coupled to an intermediate node
• Ni l itself coupled to the output node NS I associated with the transistor TR21.
• the K second conduction electrodes D2 of the K second polarization transistors respectively associated with the K second transistors TR2j, j varying from 1 to K, are respectively connected to the K intermediate nodes Nlj themselves respectively coupled to the K output nodes NSj, j varying from 1 to K.
• Said second amplifier in this example comprises a second input transistor TRE2, mounted as a common source, the gate of which is coupled to said input BE of the second amplifier.
• the second input transistor TRE2 has a first conduction electrode, here the source S, connected to the reference supply terminal GND and a second conduction electrode, here the drain D, coupled to the output BS of the second amplifier by through a cascode transistor TRC2, the gate of which is connected to the supply voltage Vdd.
• This cascode transistor TRC2 not essential, has the same advantage as that explained above for the cascode transistor TRC 1.
• the output BS of the second amplifier is coupled to a second polarization stage POL21 of conventional and known structure.
• the output BS is also coupled to the gate of the second bias transistor TRPL2.
• the second K transistors, the second amplifier and the second bias transistor are of the same type of conductivity, here the type of conductivity N. In other terms, all these transistors are NMOS transistors.
• the second negative gain amplifier will, via the source gate voltage of the second bias transistor TRPL2, bias the gate of the second transistor TR21, and will stabilize the gate voltage of the second transistor TR21 at a fixed value regardless of the value of the current flowing in this second transistor TR21, due to the negative feedback of the output terminal on its input.
• the device DIS also here includes a current mirror MR connected between the common drains D I of the first bias transistors TRPL 1 and each of the intermediate nodes Nlj.
• the current mirror MR here comprises a main PMOS transistor referenced TRP, the source of which is connected to a supply terminal intended to receive a supply voltage Vdd.
• This main transistor TRP is mounted as a diode with its gate connected to its drain.
• the drain of the transistor TRP is connected to the terminal common to the common drains D I of the first bias transistors.
• the current mirror MR also includes K secondary transistors TRSj, j varying from 1 to K, each connected between the supply voltage Vdd and the corresponding intermediate node Nlj.
• the gates of the secondary transistors TRSj are connected to the gate and to the drain of the main transistor TRP.
• the ratio between the size of the main transistor TRP and the size of each secondary transistor TRSj is equal to N, that is to say the number of first transistors TR1 i.
• this size ratio can be obtained by a size of the transistor TRP actually N times greater than the size of a secondary transistor TRSj or else for example N main transistors of size 1 and connected in parallel.
• a current Ip flows between the drain of the transistor TRP and the common drains of the first bias transistors TRPL 1.
• This current Ip is equal to the sum of the currents flowing in the first transistors TRl i.
• the outputs of the current mirror respectively deliver to the K intermediate nodes Nlj, a reference current, which is here equal to Ip / N.
• This reference current is therefore here equal to the average of the currents flowing in the first transistors TRl i.
• the current I2j passing through the second transistor TR2j can be located on one side or the other of the reference current Iref.
• This output stage comprises a first auxiliary transistor PMOS TRXP forming part of the current mirror MR and also delivering the reference current Iref to an auxiliary current mirror MRX comprising a second auxiliary transistor NMOS TRXN, mounted as a diode, and a third auxiliary transistor TRN 1 delivering on its drain, connected to the output node NSj, the reference current Iref.
• This output stage also includes a fourth auxiliary transistor PMOS TRP 1, mounted as a common source, the gate of which is connected to the intermediate node Nlj.
• the drain of transistor TRP 1 and the drain of transistor TRN1 are mutually connected and form the output node NSj.
• the output signal has a first level corresponding to a first logic value for the corresponding bit, for example the value 1. If the reference current Iref is less than the current I2j, the output signal has a second level corresponding to a second logic value for the corresponding bit, for example the value 0.
• FIG. 5 makes it possible to detect bits of the digital code delivered by the device DIS whose values may not be stable and repeatable.
• the device DIS of FIG. 2 when the device DIS of FIG. 2 is supplied, it may very well be that for certain second transistors, the currents passing through them have levels close to the level of the reference current Ief.
• the characteristics of the output stage in particular can lead to comparisons giving unstable or non-repeatable values from one energization to another.
• the logical values of the bits associated with these second transistors can switch from one power-up to another, for example due to the instability of comparison.
• FIG. 5 makes it possible to detect these bits and to make a decision as to the management of their value.
• the current mirror MR has an adjustable division ratio between several values comprising the value 1 / N and auxiliary values situated on either side of the value 1 / N.
• This secondary transistor TRS 1 has a width N times smaller than that of the main transistor TRP.
• the current mirror MR also includes in this example, four other secondary transistors TRS la, TRS lb, TRS lc and TRS ld respectively connected to said supply terminal by four other controllable switches SWl a, SWlb, SWl c and SWl d.
• the drains of these four other secondary transistors TRS la, TRS lb, TRS lc and TRS ld, are also connected to the intermediate node Ni l.
• the ratio of the width of each other secondary transistor to the width of the main transistor TRP is 1 / N +/- x%.
• the ratio between the width of the secondary transistor TRS l a and the width of the main transistor TRP is equal to 1 / N + 5%.
• the ratio between the width of the secondary transistor TRS l b and the width of the main transistor TRP is equal to 1 / N + 10%.
• the ratio between the width of the secondary transistor TRS l c and the width of the main transistor TRP is equal to 1 / N - 5%.
• the ratio between the width of the secondary transistor TRS l d and the width of the main transistor TRP is 1 / N - 10%.
• the current delivered to the intermediate node will be offset by a few percent relative to the current Iref delivered by the secondary transistor TRS 1, that is to say relative to the average of the sum of the currents flowing in the N first transistors TRl i.
• one selects for each intermediate node Nlj, one of the four switches SWl a to SW l d, for example the switch SWl b.
• the logical values of the unstable bits are for example 0.
• Processing means will then compare the digital code delivered to the output nodes NSj of the device DIS, bit by bit, so as to identify the bits whose logic values have changed between a shift to the right and a shift to the left of the reference current . These bits are considered unstable.
• These processing means may include logic circuits.
• the processing means make a decision as to the management of these unstable bits.
• a first solution consists in not taking these unstable bits into account in the digital code delivered by the device DIS.
• this decision will be stored in the DIS device.
• the device DIS can then be returned to its first state corresponding to that illustrated in FIG. 2 (secondary transistors TRSj selected with current ratio equal to 1 / N) and the decision taken as to (x) unstable bit (s) remains memorized and valid for the following.
• the production of the DIS device is obtained by conventional CMOS manufacturing methods.
• FIGS. 6 and 7 which schematically illustrate another possible variant of the invention making it possible to reduce the effects of aging of the transistors, or even to overcome them.
• the embodiments illustrated in FIGS. 2 and 5 in particular are entirely satisfactory, it turns out that the transistors TRP and TRS 1 of FIG. 2 generally age differently. Indeed, even if they have the same gate-source voltage, they respectively have different drain-source voltages.
• the transistors TRPL 1 and TRPL2 illustrated in FIG. 2 and respectively incorporated in the first means FM1 1 and the second means SM21 also exhibit different aging, which may ultimately lead to different decision-making as to the value of the output bits of the function device that is not physically clonable, and therefore to a digital code that is not perfectly repeatable from one power-up to another.
• the variant illustrated in FIGS. 6 to 7 therefore aims to reduce these aging effects, or even to overcome them, so as to more reliably propose the supply of a perfectly repeatable digital code from power-on to another of the physically non-clonable function device.
• first transistors TRl i, of the second transistor (s) TR2j, and of their first means FMl i and respective second associated means SM2j being identical to those already described with reference to FIG. 2, these structures will not be described again .
• the physically non-clonable function device DIS comprises, for each first transistor TRl i a first branch BRAl i incorporating this first transistor TRl i and the corresponding first means FM li.
• the device DIS also includes for each second transistor TR2j a second branch BRBj incorporating this second transistor and the second corresponding means SM2j.
• each first branch and each second branch are structurally identical, that is to say that they comprise structurally identical components or means even if the size of certain transistors may be different from a first branch to a second branch .
• each first branch BRAi comprises a first part BRA l i incorporating the first corresponding transistor TRl i and the first corresponding means FMl i.
• Each first branch also includes a second part BRA2C incorporating a first additional transistor TRA 1 mounted as a diode, this second part BRA2C being common to all the first branches BRAi.
• the first parts BRAl i of all the first branches BRAi are connected to this second common part BRA2C.
• each second branch BRBj comprises a first part BRB lj incorporating the second corresponding transistor TR2j and the second corresponding means SM2j and a second part BRB2j comprising a second additional transistor TRA2j mounted as a diode.
• first additional transistor TRA 1 and each second additional transistor TRA2j are configured to have the same gate-source voltage and the same drain-source voltage, even if they do not have the same size.
• the first additional transistor TRA 1 has a width N times greater than the width of each second additional transistor TRA2j.
• the device DIS comprises a first additional current mirror MRC 1 incorporating the first additional transistor TRA1 as well as another first additional transistor TRA10. These first two additional transistors TRA 1 and TRA10 have the same gate-source voltage but different respective drain-source voltages.
• the width of the first additional transistor TRA1 is N times greater than the width of the other first additional transistor TRA10.
• the first intermediate current delivers through the first additional current mirror MRC 1 is the current Iref (equal to Ip / N) algebraically increased by the offset current lof.
• this current Iref is equal to the average of the currents flowing in the N first transistors while the offset current lof is due to the fact that the first two additional transistors TRA 1 and TRA10 do not have the same drain-source voltage.
• the device DIS also comprises, associated with each second branch BRBj, a second additional current mirror MRC2j incorporating the second additional transistor TRA2j as well as another second additional transistor TRA20j.
• the two second additional transistors TRA2j and TRA20j have the same gate-source voltage but respective drain-source voltages.
• this second additional current mirror MRC2j delivers a current equal to the second current I2j algebraically increased by the offset current lof.
• this offset current is due to the fact that the two second additional transistors TRA2j and TRA20j do not have the same drain-source voltage.
• this other second additional transistor TRA20j and the other first additional transistor TRA10 have not only the same gate-source voltage but also the same drain-source voltage.
• the offset current lof delivered by each second current mirror MRC2j is equal to the offset current lof delivered by the first MRC 1 current mirror.
• this first current and this second current which will be compared at the level of the output node NSj so as to deliver a bit having a logic value dependent on the comparison of these two currents.
• the device DIS also comprises a first system of cascoded current mirrors coupled between on the one hand the first additional current mirror MRC 1 and on the other hand each output node Nlj or NSj.
• This first system of cascoded current mirrors comprises in this example a first cascoded mirror SMR10 having a division ratio of 1, coupled to the output of the first additional mirror MRC 1 and a second cascoded mirror SMRl lj also having a division ratio of 1 and connected between the output of the first SMR10 cascoded mirror and the node Nlj.
• the second cascoded mirror SMRl lj comprises in particular two PMOS transistors, referenced TRM lj and TRM2j, connected in series between the supply terminal (delivering the supply voltage Vdd) and the node Nlj.
• the second cascoded mirror SMRl lj therefore delivers to the node Nlj the first current Iref + lof equal to the first intermediate current Iref + lof delivered by the additional current MRC1 since the division ratios of the cascoded mirrors SMR10 and SMRl lj are equal to 1.
• the first cascoded mirror system also includes a third cascoded mirror SMR3j connected between the output of the first cascoded mirror SMR10 and the output node NSj.
• This third SMR3 cascoded mirror also has a division ratio equal to 1 and therefore also delivers the first current equal to Iref + lof.
• the device DIS also includes a second system of cascoded current mirrors SMR2j coupled between on the one hand each second additional mirror MRC2j and each output node Nlj.
• This second system of SMR2j cascoded mirrors has a division ratio equal to 1 and is therefore configured to copy the second current I2j + lof delivered by the second additional current mirror MRC2j.
• the current I2j passing through the second transistor TR2j can be located on one side or the other of the reference current Iref.
• This output stage comprises a first additional PMOS transistor TRP lj whose gate is connected to the intermediate node Nlj and a second additional transistor TRP2j connected between the transistor TRP lj and the node NSj, and whose gate is connected to the gate of the cascode transistor TRM2j of the SMR1 cascoded current mirror lj.
• the output stage also includes the two cascoded transistors of the current mirror SMR3j connected in series to the output node NSj.
• the output signal has a first level corresponding to a first logic value for the corresponding bit, for example the value 0.
• the output signal has a second level corresponding to a second logic value for the corresponding bit, for example the value 1.
• the embodiment of FIG. 7 makes it possible to detect bits of the digital code delivered by the DIS device whose values may not be stable and repeatable.
• the device DIS in FIG. 6 when the device DIS in FIG. 6 is supplied, it may very well be that for certain second transistors TR2j, the currents passing through them have levels close to the level of the reference current Ief.
• the characteristics of the output stage in particular can lead to comparisons giving unstable or non-repeatable values from one energization to another.
• the logical values of the bits associated with these second transistors can switch from one power-up to another, for example due to the instability of comparison.
• FIG. 7 makes it possible to detect these bits and to make a decision as to the management of their value. This can advantageously be done when the DIS device is first powered up.
• the cascoded current mirror SMR11j has an adjustable division ratio between several values comprising the value 1 and auxiliary values situated on either side of the value 1.
• the current mirror SMRllj also comprises in this example, four other cascoded transistors TRMlaj, TRMlbj, TRMlcj, TRMldj and TRM2aj, TRM2bj, TRM2cj and TRM2dj respectively connected to said supply terminal by four other controllable switches SWlaj, SWlbj, SWlcj and SWldj .
• the drains of these four other transistors TRM2aj, TRM2bj, TRM2cj and TRM2dj, are also connected to the intermediate node Nlj.
• the ratio between the width of each other transistor and the width of the transistor TRMlj is equal to 1 +/- x%.
• the ratio between the width of the transistor TRMlaj and the width of the transistor TRMlj is equal to 1 + 5%.
• the ratio between the width of the transistor TRMlbj and the width of the transistor TRMlj is equal to 1 + 10%.
• the ratio between the width of the transistor TRMlcj and the width of the transistor TRMlj is equal to 1 - 5%.
• the ratio between the width of the transistor TRMldj and the width of the transistor TRMlj is equal to 1 -10%.
• the current delivered to the intermediate node Nlj will be offset by a few percent relative to the current Iref delivered by the transistor TRMlj, that is to say relative to the average of the sum currents flowing in the first N TRli transistors.
• the first current (Iref + Iof +/- x%) delivered to the node Nlj will be offset by a few percent compared to the first intermediate current (Iref + Iof) delivered by the first additional current mirror MRC 1
• one selects for each intermediate node Nlj, one of the four switches SWl aj to SWl dj, for example the switch SWl bj.
• the logical values of the unstable bits are for example 0.
• Processing means will then compare the digital code delivered to the output nodes NSj of the device DIS, bit by bit, so as to identify the bits whose logic values have changed between a shift to the right and a shift to the left of the reference current .
• These processing means may include logic circuits.
• the processing means make a decision as to the management of these unstable bits.
• a first solution consists in not taking these unstable bits into account in the digital code delivered by the device DIS.
• the digital code will not contain these bits.
• Another solution is to give an arbitrary logical value to these unstable bits.
• this decision will be stored in the DIS device.
• the device DIS can then be returned to its first state corresponding to that illustrated in FIG. 6 (TRM transistors lj selected with current ratio equal to 1) and the decision taken as to (x ) unstable bit (s) remains memorized and valid for the following.

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• 2019
  • 2019-11-28 CN CN201980083137.9A patent/CN113228557A/zh active Pending
  • 2019-11-28 WO PCT/FR2019/000193 patent/WO2020120847A1/fr unknown
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