EP0788047A1 - Vorrichtung zur Erzeugung von Referenzstrom in einer integrierten Schaltung - Google Patents

Vorrichtung zur Erzeugung von Referenzstrom in einer integrierten Schaltung Download PDF

Info

Publication number
EP0788047A1
EP0788047A1 EP97400209A EP97400209A EP0788047A1 EP 0788047 A1 EP0788047 A1 EP 0788047A1 EP 97400209 A EP97400209 A EP 97400209A EP 97400209 A EP97400209 A EP 97400209A EP 0788047 A1 EP0788047 A1 EP 0788047A1
Authority
EP
European Patent Office
Prior art keywords
transistor
resistor
current
drain
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97400209A
Other languages
English (en)
French (fr)
Other versions
EP0788047B1 (de
Inventor
François Cabinet Ballot-Schmit Tailliet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR9601168A external-priority patent/FR2744262B1/fr
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Publication of EP0788047A1 publication Critical patent/EP0788047A1/de
Application granted granted Critical
Publication of EP0788047B1 publication Critical patent/EP0788047B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S323/00—Electricity: power supply or regulation systems
    • Y10S323/907—Temperature compensation of semiconductor

Definitions

  • the invention relates to a stable current reference device in integrated circuit. Such devices are used in particular in memory circuits, in particular for generating stable timing signals necessary for reading or writing memory cells.
  • the invention therefore relates to an intrinsically stable current reference device, without feedback to compensate for such or such variation.
  • the invention relates to a current reference device in integrated circuit with a reference resistor.
  • the device comprises a first and a second transistor of the same type of conductivity, the first having its gate and its drain connected together to a first terminal of the resistor, the second having its gate and its drain connected together to a second terminal of the resistor, and the first transistor having a threshold voltage greater than that of the second transistor, the two transistors being biased in saturated mode, the source of each of these transistors being biased at the same potential as the substrate or the well in which the transistor is made.
  • An intrinsically stable reference current is obtained in supply voltage, temperature and manufacturing process.
  • the device can be transposed from one manufacturing technology to another without simulations.
  • FIG. 1 represents the electronic diagram of a current reference device in integrated circuit according to the invention.
  • the reference resistance Rr which will be crossed by the reference current Ir.
  • a first terminal A of this resistance is connected to the drain of a first transistor Mos T1.
  • a second terminal B of the reference resistance is connected to the drain of a second Mos T2 transistor. These two transistors each have their gate connected to their drain.
  • the first transistor T1 has a higher threshold voltage than that of the second transistor T2.
  • the transistors T1 and T2 are of type N produced in a conventional technology with P substrate.
  • the transistor T2 is then of the native type while the transistor T1 is of the enriched type, in order to fulfill the condition on the threshold voltages (Vt 1 ⁇ Vt 2 ).
  • Their sources are then connected to ground.
  • the substrate P is therefore connected to the same potential as the source of the transistors T1 and T2, which has the effect of eliminating the substrate effect. There is therefore a particularly stable threshold voltage with the supply voltage.
  • a resistor R1 is connected to the drain of the first transistor T1 to draw a load current I1.
  • This bias resistor R1 may very well be connected directly to the supply voltage Vcc, as shown in dotted lines in FIG. 1, or else a bias circuit CP may be provided.
  • the two transistors T1 and T2 which are mounted as a diode are then in saturated mode and there is on their drain, the threshold voltage of the transistor.
  • the voltage V tN V tNna ' where V tN is the threshold voltage V t1 of the enriched transistor T1, of the order of 0.8 volt and V tNna is the threshold voltage V t2 of the native transistor T2, or about 0.2 volts.
  • This reference current is independent of the temperature. Indeed, according to theory and as verified in practice, the threshold voltages of the native transistor and the enriched transistor vary in parallel, of two millivolts per degree, so that their difference is practically independent of the temperature.
  • the only variation with the possible temperature of the reference current obtained by the device of the invention can only come from the reference resistance Rr.
  • This technology is that used in Mos technology with low drain doping called "LDD", and corresponding to a first implantation and slightly doped diffusion (N-) before the highly doped diffusion, to obtain a less abrupt junction profile, having better tensile strength.
  • LDD low drain doping
  • N- slightly doped diffusion
  • the variations of the characteristics due to the manufacturing process affect all the threshold voltages as well as the value of the reference resistance.
  • the variation can only arise in process from the variation of the threshold implant dose of the enriched transistor T1, since l
  • the thickness of the gate oxide is the same for the two transistors and that the threshold variation due to the initial doping operation of the substrate is found both on the native transistor and on the enriched transistor.
  • This variation can be estimated at ⁇ 10%.
  • the variation in resistance with the process is of the same order. In the worst case, the variation of the reference current due to the process is thus of the order of ⁇ 20%, which is satisfactory.
  • the polarization resistance of the device could be directly connected to the supply voltage Vcc.
  • the device then has the advantage of operating at very low voltage, since the critical path between the supply voltage and ground is given by R1, Rr, T2.
  • the charging current Il is then directly dependent on the supply voltage Vcc. If the supply voltage Vcc is varied in a range from 1.6 volts to 6 volts, the load current of the first transistor will vary greatly, with an annoying effect on the stability of the drain voltage of the first transistor and consequently on the reference current.
  • a bias circuit CP which includes a Mos T3 transistor, mounted as a diode, to impose on the load resistor R1 a transistor threshold voltage. higher than the threshold voltage of transistor T1, instead of the supply voltage Vcc.
  • a native P-type transistor is chosen to be able to bias the enriched N transistor T1.
  • the threshold voltage of a native P transistor (approximately 1.5 volts) is in fact greater than the threshold voltage of an enriched N transistor (approximately 0.8 volts).
  • an N type transistor more enriched than the transistor T1.
  • the P-type transistor T3 is biased in saturated mode by means of a resistor R2 connected to the supply voltage Vcc.
  • I1 (V tPna -V tN ) / R1.
  • the reference current Ir (V tN -V tNna ) / Rr is then practically independent of the supply voltage Vcc.
  • resistor R1 is charged from the resistor R2 and the reference resistor Rr is charged from the resistor R1. So that the current is sufficient to polarize the entire device, it is therefore necessary to choose resistors with values such as R2 ⁇ Rl ⁇ Rr. And if you want to limit the current consumption of the device, you need high resistances. In Figure 1, we have thus retained the following values: 50 kiloohms for R2, 200 kiloohms for R1 and 500 kiloohms for Rr.
  • the technology in drain extension it will be preferable to use the technology in drain extension to achieve the resistances , because it is less bulky (2000 ohms / square) than the source drain technology (typically 50 to 100 ohms / square in P + , 20 to 50 ohms / square in N +).
  • this drain-extension technology is less stable in temperature.
  • FIG. 2 thus represents another electronic diagram of a current reference device in integrated circuit according to an alternative embodiment of the invention, which makes it possible to use resistors of lower values.
  • a Mos transistor T4 is used as a follower to apply to the load resistor R1, a bias voltage independent of the supply voltage.
  • the transistor Mos T4 is of type N and connected between the supply voltage Vcc and the resistor R1.
  • This transistor T4 is controlled on its gate by the voltage imposed by the series connection of a transistor T5 mounted in direct diode (gate and drain connected) and of a transistor T6 mounted in direct diode. These two transistors T5 and T6 are connected in series between the gate of the follower transistor T4 and the ground.
  • the transistor T5 is preferably of the same type as the transistor T4 and with the same threshold voltage (to compensate as we will see).
  • the transistor T6 is of type P and native. It could be of type N. It is only necessary that its threshold voltage is greater than that of transistor T1.
  • a resistor R3 is provided between the supply voltage Vcc and the transistor T5 to bias the transistors T5 and T6 in saturated mode.
  • the transistors T4 and T5 of type N are chosen to be native, in order to have the lowest threshold voltage, which allows the device to operate at the lowest possible supply voltage. In this way we find on the terminal of the load resistor R1 connected to the transistor T4, the voltage (V F + ASPR TNNA -Vt Nna) is thus V ASPR.
  • the load current of the transistor T1 is therefore (V tPna -Vt tNna ) / R1 and is therefore very stable, as already explained previously.
  • the advantage of this variant is that in the resistor R3, only the current necessary to polarize the transistors T5 and T6 is consumed, unlike the diagram in FIG. 1 where the resistor R2 must not only polarize the transistor T3, but also provide enough current for the bias resistor R1 and the reference resistor Rr.
  • the diagram in FIG. 2 allows in practice to authorize a higher current consumption in the resistors R1 and Rr, and therefore makes it possible to lower the value of these resistances. We therefore have a reference current which can be established more quickly.
  • the resistance values are lower, one is less embarrassed in terms of size to choose to achieve at least the reference resistance in source / drain technology.
  • the temperature resistance of the device is also improved because the resistors are more doped. We could realize the load resistance R1 in source / drain diffusion also, but this has a less impact on the stability.
  • Figure 3 shows a variant of the device of Figure 2, which further improves the stability of the reference current.
  • the resistor R3 is directly supplied by the logic supply voltage of the circuit. If the supply voltage varies, for example if it increases, there is an effect on the gate of the follower transistor T4, which will tend to increase the reference current Ir.
  • a resistor R4 is interposed between the supply voltage Vcc and the terminal C of the resistor R3.
  • a branch identical to the branch (T5, T6) is provided between terminal C and ground, comprising two transistors T8 and T9.
  • the transistor T8 is mounted as a diode and identical to the transistor T5.
  • the transistor T9 is mounted as a diode and identical to the transistor T6. In the example they are all of the same enriched type N and of the same geometry (W / L). What is important in practice is that two by two, T5 and T8, T6 and T9, are identical to have the expected compensation.
  • This branch (T8, T9) serves as a voltage limiter at node C, to make this node less dependent on variations in the supply voltage Vdd.
  • node C When the device is switched on, node C follows the increase in the supply voltage by through resistance R4. But as soon as node C reaches a potential of the order of 2 x Vt n (sum of the threshold voltages of transistors T8 and T9 in series), the branch T8, T9, tends to maintain this level at node C: the voltage Vc will then move much less, as shown in Figure 4. Indeed T8 and T9 do not have the resistance R3 in their branch, they will pass more current (I) than T5 and T6. Thus the voltage on this branch given by Vt8 + Vt9 + Ron.I, where Ron is the equivalent pass resistance of the two transistors, will always be slightly higher than Vt5 + Vt6 (Vti is the threshold voltage of the transistor Ti).
  • the device shown can very well be produced in NMOS technology.
  • transistors for energizing the device have also been shown.
  • these transistors are not compulsory.
  • a reference current Ir is obtained, from which other reference currents can be obtained, by mirrored arrangements of current.
  • Such an arrangement is for example shown in FIG. 2: an N-type and native T7 transistor is mounted as a current mirror with respect to the transistor T2: its gate is controlled by the gate of the transistor T2.
  • Another reference resistor Rr ' is connected to the drain of transistor T7 on one terminal. The other terminal is connected to the supply voltage Vcc.
  • the same manufacturing technology will preferably be used for the reference resistors.
  • a stable reference current Ir ' is obtained. In particular, it has been possible to verify in practice that the evolution of the voltage at the drain of transistor T7 with the supply voltage Vcc is perfectly parallel between 1.6 and 6 volts.
  • a long channel T7 transistor is preferably chosen, for example with a channel length greater than 5 microns in 1 micron technology, to overcome short channel effects which affect current stability in saturated mode (with a long channel, the saturation current no longer depends on the drain-source voltage).
  • the integrated circuit current reference device therefore offers great stability. And by its design without feedback, it is transposable from a technology of manufacturing to the other without simulations, which is not the least of its advantages.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
EP97400209A 1996-01-31 1997-01-29 Vorrichtung zur Erzeugung von Referenzstrom in einer integrierten Schaltung Expired - Lifetime EP0788047B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR9601168A FR2744262B1 (fr) 1996-01-31 1996-01-31 Dispositif de reference de courant en circuit integre
FR9601168 1996-01-31
FR9607705A FR2744263B3 (fr) 1996-01-31 1996-06-20 Dispositif de reference de courant en circuit integre
FR9607705 1996-06-20

Publications (2)

Publication Number Publication Date
EP0788047A1 true EP0788047A1 (de) 1997-08-06
EP0788047B1 EP0788047B1 (de) 1998-10-07

Family

ID=26232490

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97400209A Expired - Lifetime EP0788047B1 (de) 1996-01-31 1997-01-29 Vorrichtung zur Erzeugung von Referenzstrom in einer integrierten Schaltung

Country Status (4)

Country Link
US (1) US5903141A (de)
EP (1) EP0788047B1 (de)
DE (1) DE69700031T2 (de)
FR (1) FR2744263B3 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106527558A (zh) * 2016-12-23 2017-03-22 长沙景美集成电路设计有限公司 一种低功耗的与绝对温度成正比的电流源电路

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2749939B1 (fr) * 1996-06-13 1998-07-31 Sgs Thomson Microelectronics Detecteur de gamme de tension d'alimentation dans un circuit integre
EP0943975B1 (de) * 1998-03-16 2005-06-08 STMicroelectronics S.r.l. Polarisationsspannungssteuerschaltung für schwebende Senke in einer integrierten Halbleiterschaltung
US6175267B1 (en) * 1999-02-04 2001-01-16 Microchip Technology Incorporated Current compensating bias generator and method therefor
JP2001332696A (ja) * 2000-05-24 2001-11-30 Nec Corp 基板電位検知回路及び基板電位発生回路
US6424205B1 (en) * 2000-08-07 2002-07-23 Semiconductor Components Industries Llc Low voltage ACMOS reference with improved PSRR
US6750699B2 (en) * 2000-09-25 2004-06-15 Texas Instruments Incorporated Power supply independent all bipolar start up circuit for high speed bias generators
US6346803B1 (en) * 2000-11-30 2002-02-12 Intel Corporation Current reference
US6433624B1 (en) 2000-11-30 2002-08-13 Intel Corporation Threshold voltage generation circuit
US6693332B2 (en) * 2001-12-19 2004-02-17 Intel Corporation Current reference apparatus
JP2003347852A (ja) * 2002-05-24 2003-12-05 Toshiba Corp バイアス回路及び半導体装置
US20050003764A1 (en) * 2003-06-18 2005-01-06 Intel Corporation Current control circuit
US7118274B2 (en) * 2004-05-20 2006-10-10 International Business Machines Corporation Method and reference circuit for bias current switching for implementing an integrated temperature sensor
US7489183B2 (en) * 2004-12-08 2009-02-10 Triquint Semiconductor, Inc. Bias control system for a power amplifier
US7768248B1 (en) 2006-10-31 2010-08-03 Impinj, Inc. Devices, systems and methods for generating reference current from voltage differential having low temperature coefficient
TWI335496B (en) * 2007-08-22 2011-01-01 Faraday Tech Corp Bandgap reference circuit
TW200910050A (en) * 2007-08-22 2009-03-01 Faraday Tech Corp Bandgap reference circuit
US9092045B2 (en) * 2013-04-18 2015-07-28 Freescale Semiconductor, Inc. Startup circuits with native transistors
CN116136704A (zh) * 2021-11-16 2023-05-19 罗姆股份有限公司 电流源电路

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0021289A1 (de) * 1979-06-19 1981-01-07 Kabushiki Kaisha Toshiba Konstantstromschaltung
EP0052553A1 (de) * 1980-11-14 1982-05-26 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux - E.F.C.I.S. Integrierte Konstantstromquelle in der CMOS-Technologie
DE3713107A1 (de) * 1986-04-18 1987-10-22 Sgs Microelettronica Spa Polarisationsschaltung fuer in mos-technologie ausgefuehrte integrierte anordnungen insbesondere des gemischt digital-analogen typs
US4999567A (en) * 1988-12-21 1991-03-12 Nec Corporation Constant current circuit
EP0687967A1 (de) * 1994-06-13 1995-12-20 STMicroelectronics S.A. Temperaturstabilisierte Stromquelle

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4978904A (en) * 1987-12-15 1990-12-18 Gazelle Microcircuits, Inc. Circuit for generating reference voltage and reference current
JPH0727424B2 (ja) * 1988-12-09 1995-03-29 富士通株式会社 定電流源回路
CA2066929C (en) * 1991-08-09 1996-10-01 Katsuji Kimura Temperature sensor circuit and constant-current circuit
JP2531104B2 (ja) * 1993-08-02 1996-09-04 日本電気株式会社 基準電位発生回路
JPH07106869A (ja) * 1993-09-30 1995-04-21 Nec Corp 定電流回路
US5739682A (en) * 1994-01-25 1998-04-14 Texas Instruments Incorporated Circuit and method for providing a reference circuit that is substantially independent of the threshold voltage of the transistor that provides the reference circuit
JP3374541B2 (ja) * 1994-08-22 2003-02-04 富士電機株式会社 定電流回路の温度依存性の調整方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0021289A1 (de) * 1979-06-19 1981-01-07 Kabushiki Kaisha Toshiba Konstantstromschaltung
EP0052553A1 (de) * 1980-11-14 1982-05-26 Societe Pour L'etude Et La Fabrication De Circuits Integres Speciaux - E.F.C.I.S. Integrierte Konstantstromquelle in der CMOS-Technologie
DE3713107A1 (de) * 1986-04-18 1987-10-22 Sgs Microelettronica Spa Polarisationsschaltung fuer in mos-technologie ausgefuehrte integrierte anordnungen insbesondere des gemischt digital-analogen typs
US4999567A (en) * 1988-12-21 1991-03-12 Nec Corporation Constant current circuit
EP0687967A1 (de) * 1994-06-13 1995-12-20 STMicroelectronics S.A. Temperaturstabilisierte Stromquelle

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106527558A (zh) * 2016-12-23 2017-03-22 长沙景美集成电路设计有限公司 一种低功耗的与绝对温度成正比的电流源电路
CN106527558B (zh) * 2016-12-23 2018-08-07 长沙景美集成电路设计有限公司 一种低功耗的与绝对温度成正比的电流源电路

Also Published As

Publication number Publication date
FR2744263B3 (fr) 1998-03-27
DE69700031T2 (de) 1999-02-25
EP0788047B1 (de) 1998-10-07
US5903141A (en) 1999-05-11
DE69700031D1 (de) 1998-11-12
FR2744263A1 (fr) 1997-08-01

Similar Documents

Publication Publication Date Title
EP0788047B1 (de) Vorrichtung zur Erzeugung von Referenzstrom in einer integrierten Schaltung
EP0578526B1 (de) Hochspannungsschaltkreis
EP0733961B1 (de) Referenzstromgenerator in CMOS-Technologie
EP0756223B1 (de) Spannungs- und/oder Stromreferenzgenerator in integriertem Schaltkreis
FR2670035A1 (fr) Circuit de production de tension de reference d'un dispositif de memoire a semiconducteurs.
EP3176669A1 (de) Schaltkreis zur erzeugung einer referenzspannung
EP1326154A1 (de) Ladungspumpe mit sehr grossem Ausgangsspannungsbereich
EP3895371A1 (de) Physikalisch unklonbare funktionsvorrichtung
FR2819652A1 (fr) Regulateur de tension a rendement ameliore
FR2832819A1 (fr) Source de courant compensee en temperature
EP1977514A1 (de) Steuerung eines mos-transistors
EP0568440B1 (de) Detektionsschaltung mit Spannungsschwellen
EP0700141A1 (de) Temperaturdetektor auf einer integrierten Schaltung
EP0649079B1 (de) Geregelter Spannungsquellengenerator der Bandgapbauart
EP1073202B1 (de) Steuerschaltung für einen Pegelumsetzer-Hochspannungsschalter
FR2678451A1 (fr) Circuit d'attaque de sortie cmos a puits flottant.
EP0687967B1 (de) Temperaturstabilisierte Stromquelle
FR2532797A1 (fr) Amplificateur differentiel
FR2514589A1 (fr) Circuit porte logique bipolaire
FR2768274A1 (fr) Circuit de generation d'une haute tension de programmation ou d'effacement d'une memoire
FR2795557A1 (fr) Dispositif d'ajustement des circuits apres mise en boitier et procede de fabrication correspondant
FR2797119A1 (fr) Dispositif de commande d'un commutateur haute tension de type translateur
FR2982720A1 (fr) Interrupteur de puissance
CH651160A5 (fr) Amplificateur differentiel a transistors bipolaires realises en technologie cmos.
FR2744262A1 (fr) Dispositif de reference de courant en circuit integre

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19971009

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 19980211

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 19981009

REF Corresponds to:

Ref document number: 69700031

Country of ref document: DE

Date of ref document: 19981112

ITF It: translation for a ep patent filed
RAP4 Party data changed (patent owner data changed or rights of a patent transferred)

Owner name: STMICROELECTRONICS S.A.

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20050110

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20050126

Year of fee payment: 9

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20050127

Year of fee payment: 9

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060129

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060131

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20060131

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20060801

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20060129

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20060929

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20070129