EP2067090B1 - Spannungsreferenz-elektronikschaltung - Google Patents

Spannungsreferenz-elektronikschaltung Download PDF

Info

Publication number
EP2067090B1
EP2067090B1 EP07820997A EP07820997A EP2067090B1 EP 2067090 B1 EP2067090 B1 EP 2067090B1 EP 07820997 A EP07820997 A EP 07820997A EP 07820997 A EP07820997 A EP 07820997A EP 2067090 B1 EP2067090 B1 EP 2067090B1
Authority
EP
European Patent Office
Prior art keywords
current
voltage
circuit
temperature
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP07820997A
Other languages
English (en)
French (fr)
Other versions
EP2067090A1 (de
Inventor
Thierry Masson
Jean-François Debroux
Pierre Coquille
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teledyne e2v Semiconductors SAS
Original Assignee
e2v Semiconductors SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by e2v Semiconductors SAS filed Critical e2v Semiconductors SAS
Publication of EP2067090A1 publication Critical patent/EP2067090A1/de
Application granted granted Critical
Publication of EP2067090B1 publication Critical patent/EP2067090B1/de
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is dc
    • G05F3/10Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to electronic integrated circuits and more specifically to the production of a temperature-independent voltage reference circuit, based on the properties of silicon bipolar transistors.
  • bandgap reference circuit The establishment of a reference voltage in a silicon integrated circuit most often comprises the realization of a circuit generically called a "bandgap reference circuit" because of the fact that it uses physical properties intrinsic silicon to ensure constant voltage despite temperature changes; the term bandgap refers to the difference in intrinsic energy that exists between the valence and conduction bands of silicon, a difference that is largely independent of temperature over a wide range of temperatures.
  • a bandgap reference circuit conventionally uses the combination of a base-emitter voltage of a transistor, which varies negatively (and approximately linearly) with the temperature, and a current or voltage that varies positively. (and almost linearly) with the temperature.
  • a base-emitter voltage of a transistor which varies negatively (and approximately linearly) with the temperature
  • a current or voltage that varies positively and almost linearly with the temperature.
  • the difference of the base-emitter voltages of two different emitter surface transistors, diode-mounted and powered by the same current sources is a voltage that varies positively with temperature.
  • bandgap reference circuits with temperature-dependent curvature corrections are given in the literature, for example: " A curvature corrected low-voltage bandgap reference "from Gunawan, Meijer, Fondrie, Huijsing in IEEE JSSC June 1993 ; or " A new Fahrenheit temperature sensor "by R. Pease in IEEE JSSC December 1984 . These corrections are complex.
  • CMOS technology circuits in which the bipolar transistors that are available to realize the voltage reference circuit, are PNP transistors of poor properties and widely dispersed characteristics from circuit to circuit. ; these transistors are in fact principally transistors that can be described as parasitic transistors formed from the P-type substrate, N-type wells of the PMOS transistors and source diffusions of these PMOS transistors.
  • transistors are in fact principally transistors that can be described as parasitic transistors formed from the P-type substrate, N-type wells of the PMOS transistors and source diffusions of these PMOS transistors.
  • the object of the invention is to propose a solution that improves the performance of the previous circuits.
  • the patent US 7,091,713 describes a bandgap type circuit with various compensations.
  • a voltage reference circuit having a first bandgap circuit providing a first order temperature stable voltage or current from a PTAT current generator providing a temperature proportional current.
  • this generator comprising, between a power supply and a ground, two parallel branches, one comprising a first MOS transistor in series with a bipolar transistor mounted diode, the other comprising a second MOS transistor identical to the first, a resistor and a second bipolar transistor having a transmitter area N times greater than the emitter area of the first, with a differential amplifier which drives the MOS transistors and which establishes in the resistor a voltage drop equal to the difference of the base voltages; emitter of the two bipolar transistors, characterized in that there is provided means for injecting at the junction point in be the first bipolar transistor and the first MOS transistor a current which is equal to the base current of the first bipolar transistor and means for injecting at the junction point of the second bipolar transistor and the resistor a current which is equal to the base current of the second bipolar transistor
  • the first bandgap circuit comprises, in addition to the current generator PTAT supplying a current proportional to the absolute temperature, means for producing a current which is the ratio between a bipolar transistor base-emitter voltage and a resistance value. this current being applied to an input of an operational amplifier of the summator.
  • the circuit (called “thermometer” circuit) providing a voltage proportional to the difference (T-Tr) preferably comprises a current generator proportional to the absolute temperature (which may be the same as the previous one), means for applying this current a resistor and a bipolar transistor, and a differential amplifier for establishing a voltage which is the difference between the base-emitter voltage of this bipolar transistor and the voltage drop across the resistor.
  • the reference temperature is preferably the ambient temperature of about 25 ° C.
  • PNP bipolar transistors T1 and T2 and PMOS transistors Q1 and Q2 form with a differential amplifier A1 the core of a current generator PTAT, that is to say a circuit providing a current proportional to the absolute temperature T.
  • Transistors T1 and T2 are of different emitter surfaces, transistor T2 having a surface N times greater than that of transistor T1.
  • Transistors Q1 and Q2 are identical and constitute variable but identical current sources. Their grids are brought to the same variable potential and their source is at a supply voltage Vdd.
  • the transistor T1 is diode-mounted between the drain of Q1 and GND mass: T1 base and collector are joined and connected to ground, the transmitter is connected to the drain of Q1.
  • the assembly is the same for T2 and Q2 but a resistor R2 is interposed between the drain of T2 and the emitter of Q2.
  • the differential amplifier A1 has its two inputs respectively connected to the drains of Q1 and Q2; it carries out a counter-reaction by acting on the common potential of the gates of these two transistors, therefore on the identical currents which cross them, until finding a point of equilibrium where the potentials of the two drains are identical (at the voltage of input offset near the amplifier).
  • the circuit of the figure 1 therefore constitutes a current generator I2 of value proportional to the absolute temperature and varying linearly and positively with the temperature.
  • a resistor R3 is connected between the drain of Q3 and the emitter of a PNP transistor T3 diode-mounted like T1 and T2, having its collector and base grounded.
  • the series assembly Q3, R3, T3 is thus mounted as the set Q2, R2, T2 and the current flowing through the resistor R3 is identical to the current I2 which flows through R2.
  • the coefficient of positive variation with temperature is (k / q) (LogN) R3 / R2.
  • the negative variation of the base-emitter voltage Vbe3 of the transistor T3 depends on the technological parameters of the transistor. It is linear in the first order, and the order of magnitude of the coefficient of variation is, for example, -2mV / ° C. It can be determined experimentally for a given technology. Therefore, by correctly choosing the resistor R3 and adding the voltage R3.I2 and the voltage Vbe of the transistor T3, it is possible to obtain a voltage having a zero overall coefficient of variation at the first order.
  • the value chosen for R3 for this purpose obviously depends on the values chosen for N and for R2 as well as on the emitter surface of transistor T3.
  • FIG. 3 Another example of embodiment is shown in the figure 3 ; this circuit works in a very similar way to that of the figure 2 and it is shown here because it is easier to use in the architecture of the present invention.
  • this example instead of adding two voltages Vbe3 and R3.12 in a branch Q3, R3, T3 as was the case in the figure 2 , two currents are added before converting the sum of these currents into a voltage EG (T).
  • T voltage EG
  • a differential amplifier A2 controls the gate of a PMOS transistor Q4 which is in series with a resistor R4, so as to pass in the resistor R4 a current such that the voltage drop in this resistor is equal to the base-emitter voltage Vbe2 of transistor T2.
  • This assembly therefore converts the voltage Vbe2 into a current Vbe2 / R4 in the resistor R4 and in the transistor Q4.
  • a PMOS transistor Q5 copies the current Vbe2 / R4 passing through Q4 (same gate voltage as Q4, same source voltage Vdd); another PMOS transistor Q6 copies the current 12 which passes into the transistor Q2 (same gate voltage as Q2, same source voltage Vdd).
  • the currents of Q5 and Q6, respectively equal to Vbe2 / R4 and 12 (kT / q) (LogN) / R2 are summed in a load resistor R6.
  • the load resistor is connected between the combined drains of Q5 and Q6 and the mass. It will be seen that the load resistor can also be an input resistor or a loopback resistor of an operational amplifier.
  • the figure 8 represents the principle of the present invention.
  • the PNP transistors may be of poor quality and in particular they may have a gain in low beta current and highly dispersed. This is particularly the case when the voltage reference circuit is made in a CMOS technology where the only available bipolar transistors are PNP transistors formed between the P-type substrate, the N-type wells and the source and drain diffusions. PMOS formed in these boxes. These transistors are of poor quality. That is why it is preferable to provide a compensation circuit of the PTAT current generator, which will be described with reference to the figure 8 .
  • the circuit represented at figure 8 includes, on its right side, the PTAT current generator of the figure 1 and on its left side the compensation circuit whose function is to inject into the emitter of the transistor T1 and into the emitter of the transistor T2 a current equal to the base current Ib which flows through these transistors when the resistor R2 is traveled. by the current 12 proportional to the absolute temperature. By injecting these currents, it is ensured that the equal currents flowing through Q1 and Q2 and thus the current I2 passing through the resistor R2 are not the emitter current of the transistors T1 and T2 but are the collector current Ic.
  • the operating equations of the PTAT generator are based on the calculation of the collector currents of the transistors T1 and T2 of different size. This does not matter when the current gain is high because the difference between the collector current and the emitter current is insignificant. This is more important when the gain is low. With the compensation introduced, the PTAT generator is actually operated from collector currents even if the gain is small.
  • the current I2 in Q1 is copied into a branch Q10, T10.
  • the transistor Q10 is identical to Q1 and has its gate and its source at the same potentials as the gate and the source of Q1.
  • Transistor T10 is identical to T1 and has its emitter connected to ground like T1.
  • the base of T10 is not connected directly to the mass as that of T1, it is connected to ground by means of a NMOS transistor Q11 mounted diode. This transistor Q11 is therefore traversed by a current Ib which is the basic current of T10, identical to the basic current of T1.
  • a transistor Q16 copies the current Ib of the transistor Q13 to inject it at the junction point of the transistors Q10 and T10.
  • the current I2 in the transistors Q1 and Q2 is indeed a collector current of the transistors T1 and T2.
  • the result is an operation in which the current proportional to the temperature is a transistor collector current and not an emitter current as in the conventional diagrams, so that it is insensitive to the fact that the current gain of PNP transistors are small and scattered.
  • the transistors were NPN.
  • This current gain compensation of the PMOS transistors of the PTAT generator can be applied to a more complex voltage reference circuit in which it is sought to compensate for the curvatures of the reference voltage variation as a function of the temperature towards the highest temperatures. or the lowest.
  • the figure 4 represents the principle of obtaining a stable reference voltage.
  • a heart circuit C1 bandgap such as that of the figure 2 or the figure 3 that is to say, using the summation of a voltage Vbe and a voltage proportional to the absolute temperature and giving a reference voltage (or a current) stable in the first order; and we add to the sum EG (T) thus obtained two other voltages, one of which, denoted by E2 (T), comes from a circuit C2 called “thermometer circuit” and the other, denoted by E3 (T) is derived from a circuit C3 of elevation squared which raises squared voltage from the thermometer circuit.
  • thermometer circuit is meant a circuit capable of establishing a voltage proportional to the difference T-Tr between the absolute temperature T and a reference temperature Tr; the temperature Tr can be the standard ambient temperature of 25 ° C.
  • the squaring circuit is, in turn, capable of establishing a voltage proportional to (T-Tr) 2 from a voltage supplied by the thermometer circuit.
  • the weighting coefficients are chosen to make the output voltage of the summator as constant as possible in the presence of temperature variations.
  • the coefficient G1 can be chosen arbitrarily equal to 1, adjustment parameters such as the value of R6 making it possible to adjust the level of EG (T).
  • EG (Tr) is a value fixed, which is the theoretical value that one would like to have at all temperatures but that in fact only has the reference temperature Tr.
  • thermometer circuit C2 and the squaring circuit C3 are intended to compensate for these output voltage variations of the circuit C1.
  • circuit C1 supplies an output current rather than a voltage EG (T)
  • this current is converted into voltage in a resistor of the adder ADD.
  • the coefficients G2 and G3 are negative if a, b, k1 and k2 are positive. But it must be provided in particular that the signs of a and b may be arbitrary, and it will be provided that the coefficients G2 and G3 may be of negative sign (or alternatively that the outputs E2 (T) and E3 (T) may be have an inverted sign if necessary).
  • the figure 5 is a practical diagram taking up the heart of the bandgap circuit of the figure 3 and showing how one can perform the desired linear combination using an operational amplifier and several summing resistors.
  • the circuit C1 supplies an output current which is the sum of the currents flowing in the transistors Q5 and Q6: (kT / q) (LogN) / R2 + Vbe2 / R4
  • the other input E2 of the amplifier is brought to a reference potential VG (which may be the ground GND or preferably the midpoint between the low supply GND and the high supply Vdd).
  • the potential VG is, as will be seen, the reference with respect to which the thermometer circuit C2 provides a voltage proportional to T-Tr, and the circuit C3 provides a voltage proportional to the square of T-Tr. That is why this potential must also serve as a reference in the adder ADD placed at the output of the circuit C1.
  • the loopback resistor Rs1 converts the current passing through it into voltage (like the resistor R6 of the figure 3 ).
  • the current flowing through it is such that the sum of the currents entering on the node E1 is zero.
  • This sum comprises the currents originating from transistors Q5 and Q6 (currents Vbe2 / R4 and 12), the current in resistor Rs1 and two currents injected, through a resistor Rs2 and a resistor Rs3 respectively, by the voltage outputs of the thermometer circuit.
  • the resistor Rs2 defines the weighting coefficient G2 corresponding to the circuit C2.
  • This resistor Rs2 is placed between the output of the circuit C2 and the input E1 of the operational amplifier AO.
  • the circuits C2 and C3 provide low output impedance voltages and impose their output potential on the resistors Rs2 and Rs3.
  • the circuits C2 and C3 provide referenced voltages with respect to the voltage VG.
  • the circuit C2 provides a voltage E2 (T) which is equal to k2 (T-Tr).
  • the circuit C3 provides a voltage E3 (T) which is equal to k3 (T-Tr) 2 .
  • the operation of the operational amplifier is conventional: the sum of the currents arriving at its input E1 is zero, and the voltage at this input is equal to the voltage at the input E2, that is to say at VG.
  • Vref the output voltage (referenced with respect to the reference potential VG) of the amplifier AO
  • Vref the output voltage (referenced with respect to the reference potential VG) of the amplifier AO
  • Vref - Rs ⁇ 1 ⁇ I ⁇ 2 + Vbe / 4 - E ⁇ 2 T ⁇ Rs ⁇ 1 / Rs ⁇ 2 - E ⁇ 3 T ⁇ Rs ⁇ 1 / Rs ⁇ 3
  • Rs1 is set in principle according to the value that it is desired to give to the reference voltage Vref at the reference temperature Tr. This value is -Rs1 [I2 + Vbe2 / R4] measured at the reference temperature and which is EG (Tr) according to the notation previously used.
  • thermometer circuit C2 can be constituted for example as follows, as shown in FIG. figure 6 it comprises a current generator proportional to the absolute temperature (PTAT); this generator can be the one used in the circuit C1 to establish the current or the constant voltage to the first order. It is therefore composed of PNP transistors T1, T2, differential amplifier A1, resistor R2, and current sources constituted by PMOS transistors Q1, Q2 whose gates are connected to the output of differential amplifier A1. .
  • PTAT absolute temperature
  • the current I2 proportional to the absolute temperature is copied by a PMOS transistor Q7 and a PMOS transistor Q8 which both have the same source and gate potential as Q1 and Q2.
  • Transistor Q7 supplies a resistor R7.
  • the resistor R7 is connected between the drain of the transistor Q7 and the output of a differential amplifier A3.
  • Transistor Q8 feeds a diode-mounted bipolar transistor T8 having its emitter connected to the drain of Q8 and its collector and base connected to the reference potential VG.
  • the differential amplifier A3 has a first input connected to the point of junction of R7 and Q7 and a second input connected to the junction point of Q8 and T8.
  • the differential amplifier A3 establishes a voltage which is the difference between the base-emitter voltage of this bipolar transistor (traversed by a current proportional to the temperature) and the voltage drop across the resistor (traversed by a current proportional to the temperature).
  • the resistor R7 is adjustable to adjust the thermometer circuit such that the output voltage E2 (T) is zero for the reference temperature Tr, that is to say that the output of the amplifier A3 is equal at VG for this temperature.
  • an additional operational amplifier mounted in an analog inverter can be provided at the output of the amplifier A3.
  • the output of the additional amplifier or the output of the amplifier A3 will be used according to the sign of a, the choice being made during the circuit test; the adjustment of the resistance R7 is also done during the test.
  • thermometer circuit To produce a signal proportional to (T-Tr) 2 the thermometer circuit is used, and its output voltage E2 (T) is applied to a squaring circuit which uses the same potential reference VG.
  • a current equal to the difference between the current of the source SC3 and the current of the transistor Q30 is extracted from the junction point between the source SC3 of value Io and the drain of transistor Q30. This difference is equal to [E2 (T)] 2 /4.(R21) 2 .Io
  • the voltage E3 (T) is practically proportional to the square of E2 (T), therefore to the square of T-Tr, provided, however, that Io is approximately independent of the temperature. To obtain this result, it is arranged to realize the current sources of value Io and 2Io from the ratio between a voltage approximately independent of the temperature and a bias resistor Rpol.
  • the voltage approximately independent of the temperature is preferably the output voltage EG from the bandgap circuit core.
  • an inverting operational amplifier can be placed at the output of the amplifier A4. The output of one or the other of these amplifiers will be chosen on the test.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • Power Engineering (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Control Of Charge By Means Of Generators (AREA)
  • Details Of Television Scanning (AREA)

Claims (6)

  1. Spannungsreferenzschaltung, die eine erste Schaltung (C1) des Bandlückentyps umfasst, die eine(n) temperaturstabile(n) Spannung oder Strom der ersten Ordnung von einem Stromgenerator PTAT erzeugt, der einen zur absoluten Tempertur proportionalen Strom liefert, wobei dieser Generator zwischen einer Einspeisung (Vdd) und einer Masse (GND) zwei parallele Zweige umfasst, von denen der eine einen ersten MOS-Transistor (Q1) in Reihe mit einem diodengeschalteten bipolaren Transistor (T1) und der andere einen zweiten, mit dem bipolaren Transistor (T1) identischen MOS-Transistor (Q2) umfasst, wobei der Stromgenerator PTAT darüber hinaus einen Widerstand (R2) und einen zweiten bipolaren Transistor (T2) mit einer Emitterfläche umfasst, die N mal größer ist als die Emitterfläche des ersten, mit einem Differentialverstärker (A1), der die MOS-Transistoren steuert und in dem Widerstand einen Spannungsabfall erzielt, der gleich der Differenz der Basis-Emitter-Spannungen der beiden bipolaren Transistoren ist, dadurch gekennzeichnet, dass sie mit Mitteln zum Injizieren eines Stroms an der Übergangsstelle zwischen dem ersten bipolaren Transistor (T1) und dem ersten MOS-Transistor (Q1), der gleich dem Basisstrom des ersten bipolaren Transistors (T1) ist, und mit Mitteln zum Injizieren eines Stroms an der Übergangsstelle zwischen dem zweiten bipolaren Transistor (T2) und dem Widerstand (R2) ausgestattet ist, der gleich dem Basisstrom des zweiten bipolaren Transistors (T2) ist, so dass der Ausgangsstrom des Generators von Strom proportional zur Temperatur gleich dem Kollektorstrom und ungleich dem Emitterstrom des zweiten bipolaren Transistors (T2) ist.
  2. Referenzschaltung nach Anspruch 1, dadurch gekennzeichnet, dass die erste Schaltung des Bandlückentyps eine(n) temperaturstabile(n) Spannung oder Strom erzeugt von:
    - einer Basis-Emitter-Spannung des bipolaren Transistors (T3) mit einer von der Temperatur abhängigen negativen Variationssteigung,
    - und dem Strom (I2) vom Generator PTAT.
  3. Referenzschaltung nach Anspruch 1, dadurch gekennzeichnet, dass sie einen Differentialverstärker (A2) und einen von diesem Differentialverstärker gesteuerten dritten MOS-Transistor (Q4) umfasst, um in einem Widerstand (R4) mit dem Wert R4 einen Strom von gleich Vbe2/R4 zu erzielen, wobei Vbe2 die Basis-Emitter-Spannung des zweiten Transistors ist.
  4. Referenzschaltung nach Anspruch 3, dadurch gekennzeichnet, dass sie wenigstens einen vierten und einen fünften Transistor (Q5, Q6) umfasst, um den Strom in dem Widertand mit dem Wert R4 und den Strom in dem Widerstand mit dem Wert R2 zu duplizieren.
  5. Referenzschaltung nach einem der vorherigen Ansprüche, dadurch gekennzeichnet, dass sie ein Addierglied (ADD) zum Erzielen einer linearen Kombination mit den jeweiligen Gewichtungskoeffizienten von drei Werten umfasst, die jeweils die Folgenden sind:
    - die/der Ausgangsspannung oder -strom (EG(T)) der ersten Bandlückenschaltung (C1),
    - die/der Ausgangsspannung oder -strom einer zweiten Schaltung (C2), die eine Spannung (E2(T)) oder einen Strom proportional zur Differenz zwischen der absoluten Temperatur T und einer Referenztemperatur Tr liefert,
    - die/der Ausgangsspannung oder -strom (E3(T)) einer dritten Schaltung (C3), die eine Spannung oder einen Strom proportional zum Quadrat dieser Differenz liefert.
  6. Referenzschaltung nach Anspruch 5, dadurch gekennzeichnet, dass die zweite Schaltung (C2), die eine Spannung proportional zur Differenz T-Tr liefert, Folgendes umfasst: einen Generator von Strom proportional zur absoluten Temperatur, Mittel zum Zuführen dieses Stroms zu einem Widerstand mit dem Wert R7 und zu einem bipolaren Transitor (T8), und einen Differentialverstärker zum Erzielen einer Spannung, die die Differenz zwischen der Basis-Emitter-Spannung (Vbe8) dieses bipolaren Transistors und dem Spannungsabfall an den Anschlüssen dieses letzteren Widerstands (R7) ist.
EP07820997A 2006-10-06 2007-10-05 Spannungsreferenz-elektronikschaltung Not-in-force EP2067090B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0608789A FR2906903B1 (fr) 2006-10-06 2006-10-06 Circuit electronique de reference de tension.
PCT/EP2007/060624 WO2008040817A1 (fr) 2006-10-06 2007-10-05 Circuit electronique de reference de tension

Publications (2)

Publication Number Publication Date
EP2067090A1 EP2067090A1 (de) 2009-06-10
EP2067090B1 true EP2067090B1 (de) 2010-07-28

Family

ID=37909068

Family Applications (1)

Application Number Title Priority Date Filing Date
EP07820997A Not-in-force EP2067090B1 (de) 2006-10-06 2007-10-05 Spannungsreferenz-elektronikschaltung

Country Status (6)

Country Link
US (1) US20100007324A1 (de)
EP (1) EP2067090B1 (de)
AT (1) ATE475925T1 (de)
DE (1) DE602007008115D1 (de)
FR (1) FR2906903B1 (de)
WO (1) WO2008040817A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2975510B1 (fr) * 2011-05-17 2013-05-03 St Microelectronics Rousset Dispositif de generation d'une tension de reference de bande interdite ajustable a fort taux de rejection d'alimentation
FR2975512B1 (fr) * 2011-05-17 2013-05-10 St Microelectronics Rousset Procede et dispositif de generation d'une tension de reference ajustable de bande interdite
CN103026311B (zh) * 2011-05-20 2015-11-25 松下知识产权经营株式会社 基准电压生成电路及基准电压源
JP6242274B2 (ja) * 2014-04-14 2017-12-06 ルネサスエレクトロニクス株式会社 バンドギャップリファレンス回路及びそれを備えた半導体装置
US9864389B1 (en) * 2016-11-10 2018-01-09 Analog Devices Global Temperature compensated reference voltage circuit
US11740281B2 (en) 2018-01-08 2023-08-29 Proteantecs Ltd. Integrated circuit degradation estimation and time-of-failure prediction using workload and margin sensing
US11068011B2 (en) * 2019-10-30 2021-07-20 Taiwan Semiconductor Manufacturing Company Ltd. Signal generating device and method of generating temperature-dependent signal
DE102021112735B3 (de) 2021-05-17 2022-08-04 Infineon Technologies Ag Bandabstandsreferenz-schaltung
US11619551B1 (en) * 2022-01-27 2023-04-04 Proteantecs Ltd. Thermal sensor for integrated circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391980A (en) * 1993-06-16 1995-02-21 Texas Instruments Incorporated Second order low temperature coefficient bandgap voltage supply
US5629612A (en) * 1996-03-12 1997-05-13 Maxim Integrated Products, Inc. Methods and apparatus for improving temperature drift of references
US6255807B1 (en) * 2000-10-18 2001-07-03 Texas Instruments Tucson Corporation Bandgap reference curvature compensation circuit
US20030117120A1 (en) * 2001-12-21 2003-06-26 Amazeen Bruce E. CMOS bandgap refrence with built-in curvature correction
US7088085B2 (en) * 2003-07-03 2006-08-08 Analog-Devices, Inc. CMOS bandgap current and voltage generator
US7091713B2 (en) * 2004-04-30 2006-08-15 Integration Associates Inc. Method and circuit for generating a higher order compensated bandgap voltage
US7486065B2 (en) * 2005-02-07 2009-02-03 Via Technologies, Inc. Reference voltage generator and method for generating a bias-insensitive reference voltage
TWI256725B (en) * 2005-06-10 2006-06-11 Uli Electronics Inc Bandgap reference circuit

Also Published As

Publication number Publication date
ATE475925T1 (de) 2010-08-15
US20100007324A1 (en) 2010-01-14
FR2906903B1 (fr) 2009-02-20
DE602007008115D1 (de) 2010-09-09
WO2008040817A1 (fr) 2008-04-10
FR2906903A1 (fr) 2008-04-11
EP2067090A1 (de) 2009-06-10

Similar Documents

Publication Publication Date Title
EP2067090B1 (de) Spannungsreferenz-elektronikschaltung
EP0424264B1 (de) Stromquelle mit niedrigem Temperaturkoeffizient
EP0733961B1 (de) Referenzstromgenerator in CMOS-Technologie
FR2623307A1 (fr) Source de courant a deux bornes avec compensation de temperature
EP1380914A1 (de) Referenzspannungsquelle, Temperatursensor,Temperaturschwellendetektor, Chip und entsprechendes System
FR2975510A1 (fr) Dispositif de generation d'une tension de reference de bande interdite ajustable a fort taux de rejection d'alimentation
FR2975512A1 (fr) Procede et dispositif de generation d'une tension de reference ajustable de bande interdite
CH642451A5 (fr) Dispositif detecteur de temperature.
FR2465355A1 (fr) Circuit generateur de tension de reference de bande interdite
EP0438363A1 (de) Strommess-Schaltung in einem MOS-Leistungstransistor
FR2912013A1 (fr) Dispositif de generation de courant de polarisation ayant un coefficient de temperature ajustable.
CH697322B1 (fr) Procédé de génération d'un courant sensiblement indépendent de la température et dispositif permettant de mettre en oeuvre ce procédé.
EP1566717B1 (de) Vorrichtung zur Erzeugung einer verbesserten Referenzspannung und entsprechende integrierte Schaltung
FR2887650A1 (fr) Circuit fournissant une tension de reference
FR2466135A1 (fr) Amplificateurs operationnels de transconductance
FR2832819A1 (fr) Source de courant compensee en temperature
FR2809833A1 (fr) Source de courant a faible dependance en temperature
FR2825806A1 (fr) Circuit de polarisation a point de fonctionnement stable en tension et en temperature
EP0649079B1 (de) Geregelter Spannungsquellengenerator der Bandgapbauart
FR2890239A1 (fr) Compensation des derives electriques de transistors mos
FR2801145A1 (fr) Circuit d'alimentation a courant constant
EP0524294B1 (de) Verstärkerschaltung mit exponentieller verstärkungssteuerung
FR2677822A1 (fr) Amplificateur differentiel.
FR2757964A1 (fr) Regulateur de tension serie
FR2969328A1 (fr) Circuit de generation d'une tension de reference sous une faible tension d'alimentation

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20090410

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA HR MK RS

17Q First examination report despatched

Effective date: 20091117

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

DAX Request for extension of the european patent (deleted)
GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: FRENCH

REF Corresponds to:

Ref document number: 602007008115

Country of ref document: DE

Date of ref document: 20100909

Kind code of ref document: P

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20100728

LTIE Lt: invalidation of european patent or patent extension

Effective date: 20100728

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101129

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101128

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101028

REG Reference to a national code

Ref country code: IE

Ref legal event code: FD4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101029

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

BERE Be: lapsed

Owner name: E2V SEMICONDUCTORS

Effective date: 20101031

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101031

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20101108

26N No opposition filed

Effective date: 20110429

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602007008115

Country of ref document: DE

Effective date: 20110429

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101031

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111031

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111031

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20101005

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110129

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20100728

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20121005

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20121005

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 10

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 11

REG Reference to a national code

Ref country code: DE

Ref legal event code: R081

Ref document number: 602007008115

Country of ref document: DE

Owner name: TELEDYNE E2V SEMICONDUCTORS SAS, FR

Free format text: FORMER OWNER: E2V SEMICONDUCTORS, SAINT EGREVE, FR

REG Reference to a national code

Ref country code: FR

Ref legal event code: CD

Owner name: TELEDYNE E2V SEMICONDUCTORS SAS, FR

Effective date: 20180907

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20181029

Year of fee payment: 12

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20181025

Year of fee payment: 12

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602007008115

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200501

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20191031