EP0481703B1 - Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung - Google Patents
Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung Download PDFInfo
- Publication number
- EP0481703B1 EP0481703B1 EP91309424A EP91309424A EP0481703B1 EP 0481703 B1 EP0481703 B1 EP 0481703B1 EP 91309424 A EP91309424 A EP 91309424A EP 91309424 A EP91309424 A EP 91309424A EP 0481703 B1 EP0481703 B1 EP 0481703B1
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- EP
- European Patent Office
- Prior art keywords
- electronic components
- conductive
- data
- interconnect
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
- G01R31/318538—Topological or mechanical aspects
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/30—Accessing single arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
Definitions
- This invention relates to an interconnect substrate with circuits mounted on the substrate for the electrical programming in the field of interconnects on the substrate and for the testing of the integrity of the interconnects, the electronic components on the substrate and the system function for hybrid circuits and multichip modules.
- Hybrid circuits and multichip modules are commonly used to connect electronic components for applications in instruments, computers, telecommunication equipment and consumer electronic products which require higher density and performance than the capabilities of printed-circuit boards.
- an engineer will design a hybrid circuit or a multichip module to carry the types of electronic components (including integrated circuits, transistors, and discrete components such as resistors, capacitors and inductors) necessary to implement the desired electronic function and to fit in the space available for the product. Consequently, each hybrid circuit or multichip module typically is custom designed.
- To design a custom hybrid circuit or a multichip module is expensive, takes time and requires custom tooling and the fabrication of prototype interconnect substrates. If errors are found in the prototypes, then the interconnect substrate must be redesigned.
- Such a process often delays the planned introduction of a new product.
- Bare dice, surface-mounted packages and electronic components are used with hybrid circuits and multichip modules, to provide high density. Shorter connection traces result in lower capacitances to drive shorter signal propagation delays, and higher performance. Testing of the integrity of the interconnects and the electronic components in the hybrid circuits and multichip modules is rather difficult. Attaching the probes of oscilloscopes and logic analyzers to observe the waveforms on the various pins of the electronic components during operation require microprobing of fine lines and pads which is difficult. Many of the interconnects to be tested are imbedded and difficult to test. The use of test pads to access some of the imbedded traces takes area and often unintentionally overlooks important traces. The testing, diagnosis and debugging of hybrid circuits and multichip modules are complicated, time consuming and often delay the planned product introduction.
- EP-A-419232 Disclosed in earlier European Patent Application 90310252.3 filed September 19, 1990 and published as EP-A-419232 is a printed circuit board of unique configuration combined with one or more special programmable integrated circuit chips (often called “programmable interconnect chips” or “PICs”) to provide a user programmable printed circuit board capable of being used to provide any one of a plurality of functions.
- PICs programmable interconnect chips
- the active circuits in the programmable interconnect chips also provide test ports which offer powerful structures for testing the integrity of the interconnects, the electronic components and the system function.
- the field programmable printed circuit board described in EP-A-419232 substantially reduces the cost associated with developing complex electronic systems by providing a standard PC board configuration which is easily and economically manufactured.
- the designer of electronic systems utilizing the standard programmable PC board described therein will also utilize computer aided design software to determine the optimum placement of the electronic components on the programmable PC board and to determine the configuration of the programmable interconnect chip or chips to properly interconnect the electronic components so as to yield the desired electronic system.
- Interconnect structure in which logic chips mounted on one or more circuit boards are programmably interconnected by interconnect chips for simulating a desired electronic design.
- the interconnect structure contains stimulators and samplers.
- a stimulator is a bit of storage controlled by a host computer for driving a net in the design being simulated.
- a sampler is a bit of storage controlled by the host computer for receiving a net in the design.
- the simulators and samplers are formed with flip-flops contained in the logic chips.
- interconnect substrates for hybrid circuits and multichip modules with circuits mounted on the substrate are disclosed. These circuits enable the engineer by using external leads to electrically program the interconnects in the field and to connect any sets of nodes on the substrate to external test ports to test the integrity of the interconnects and the electronic components on the substrate and the system function. These circuits provide the benefits of the field programmable printed-circuit boards for applications requiring the density and performance of multichip modules and hybrid circuits. During normal operation these circuits mounted on the substrate can be disabled and the connections of the interconnects on the substrate provide the desired function.
- a structure comprising: an interconnect substrate; a plurality of component contacts formed over the interconnect substrate for receipt of electronic components; a plurality of electrically conductive traces formed over the interconnect substrate, each conductive trace being electrically connected to a corresponding one of the component contacts; and at least one programmable integrated circuit mounted over a selected portion of the interconnect substrate, the or each programmable integrated circuit containing (a) a plurality of electrically conductive leads each being electrically connected to a corresponding one of the conductive traces, (b) programmable means for selectively electrically interconnecting the conductive leads so as to programmably interconnect selected ones of the conductive traces, and (c) active test devices for testing the conductive leads and/or the conductive traces and/or the electronic components received by the component contacts, the active test devices comprising sampling means to sample test data provided from the electronic components.
- the invention thus provides an architecture of interconnects on a substrate suitable for hybrid circuits and multichip modules with circuits mounted on the substrate to allow the user to electrically program the interconnects in the field with external leads and without the need to use fine probes to access internal fine lines or pads on the substrate.
- Circuits mounted on the substrate enable any set of nodes on the substrate to be connected to a test port to functionally test any component on the field programmable hybrid circuit or multichip module as well as to test the internal nodes and operation of the module and the interconnect integrity of the field programmed hybrid circuit or multichip module.
- the field programmability and testability features and ports of the resulting hybrid circuit or multichip module are enabled by mounting programmable interconnect chips ("PICs") on the substrate which contains multilayer interconnects and pads. These circuits are activated, as needed, to implement the programming in the field, or the testing functions. During normal operation, these active circuits can be disabled.
- PICs programmable interconnect chips
- An embodiment of this invention uses an interconnect substrate formed of any one of a number of materials to contain a plurality of conductive traces which are routed to a portion of the interconnect substrate on which one or more programmable interconnect chips are to be mounted.
- the interconnect substrate can for example comprise a semiconductor material such as silicon, metal (with appropriate insulating layers formed thereon) or ceramic.
- the structure of the conductive traces formed on the interconnect substrate is as described in EP-A-419232.
- the interconnect substrate can contain a single or multiple layers as described in EP-A-419232.
- the PIC mounted on the interconnect substrate performs the functions of programming and testing.
- Bonding pads on the substrate are distributed in a regular pattern to make the bonding pads as general purpose as possible to be used with different dice and electronic components. Moreover, the pad layout is independent of die attach and bonding schemes (for example, wire bonding, solder bumps or TAB).
- Figure 1 illustrates an embodiment of the interconnect substrate 1001 of this invention where the active circuits for the electrical programming and the testing of the interconnects is implemented with a programmable interconnect chip ("PIC") 1005 mounted thereon.
- PIC programmable interconnect chip
- Substrate 1001 could comprise any one of a number of materials, such as silicon, metal or ceramic, provided the materials would allow the electrical leads 1003-r,c (where r equals the number of rows of conductive pads on the interconnect substrate and c equals the number of columns of conductive pads on the interconnect substrate) to be electrically isolated from each other and thereby avoid short circuits or other unwanted electrical connections between the conductive leads 1003-r,c.
- substrate 1001 can comprise a single layer or multiple layers of support material. Shown in Figure 1 are two layers 1001-1 and 1001-2 of support material. other numbers of layers can be used if desired.
- Each layer 1001-i is fabricated of, for example, a rigid support material such as a ceramic, a metal with appropriate insulation formed on the surface thereof, or silicon with an appropriate insulation layer formed on its surface.
- the leads 1003-r,c comprise any appropriate conductive material such as, for example a metal, a silicide, doped conductive silicon or other appropriate conductive material.
- Chip 1005 contains a plurality of devices (for example, programmable devices, diodes or transistors) which can be programmed by a user to interconnect selected ones of leads 1003-r,c so that the components mounted on the interconnect substrate 1001 are properly interconnected into the desired circuit.
- the PIC chip 1005 can contain any appropriate number of interconnect structures and in fact can be one of several such PIC chips. A more detailed description of this chip is given in the above referenced EP-A-419232.
- Figures 2a and 2b illustrate PIC 1005 of Figure 1 with examples of circuits and structures for testing the integrity of the conductive interconnects, the electronic components and the system function.
- FIG. 2a shows the block diagram and active circuits on the PIC 1005 to implement a software-controlled bed-of-nails test structure.
- a typical cell 406-s,t on the PIC 1005 with a configuration of pads 407-m is shown. Each pad 407-m is connected to a corresponding conductive segment 409-m.
- Active transistors 403-m and selection/multiplexing circuits 405B also formed in PIC 1005 select any sets of pads 407 and connect them to an internal bus 414.
- breaklines are included to indicate that the PIC 1005 is only partially shown with interior portions of PIC 1005 removed for clarity.
- the signals applied on the control port can select any sets of pads 407 and connect them to the external leads of the test port.
- the user can observe the real-time waveforms or force input signals on any sets of pads connected to the test port, making it equivalent to a software-controlled bed-of-nails test structure.
- Figure 2b shows the block diagram and active circuits on the PIC 1005, to implement an imbedded logic analyzer test structure.
- key information supplied by the user is stored in the trigger data register 441.
- the comparator 442 initiates the memory controller 444 to start the memory address counter 446 for the storage memory 443 to store the sampled data from the pads 407 by the sampling gates 440.
- suitable sampled data is stored in the memory 443, the data is shifted through the test port externally to display and analyze.
- conductive leads in different layers may be interconnected, those skilled in the art will recognize that conductive leads in the same layer can be connected together using an antifuse technique. To do this, a conductive lead that has been split into two or more segments can be rejoined together by applying a programming voltage between the terminals of a programming element such as an antifuse connected to the ends of the segments of the conductive lead. This programming voltage would then cause the programming element to form a conductive path between these two ends of the conductive track.
- various segments of adjacent conductive leads can be interconnected by programming elements connected between sections of these adjacent segments. These programming elements can, in one embodiment, consist of sections of segments deliberately formed close together by, for example, introducing curves or bends in the leads.
- an embodiment of this invention uses an interconnect substrate formed of any one of a number of materials to contain a plurality of conductive traces which are routed to a portion of the interconnect substrate on which one or more programmable interconnect chips (PICs) are to be mounted.
- the interconnect substrate can, for example, comprise silicon (intrinsic or appropriately covered with an insulating layer), metal (with appropriate insulating layers formed thereon) or ceramic.
- the structure of the conductive traces formed on the interconnect substrate is as described in EP-A-419232.
- the interconnect substrate can contain a single or multiple layers of conductive traces as described in EP-A-419232.
- the PIC mounted on the interconnect substrate performs the functions of programming and testing.
- the PIC typically an integrated circuit, consists of conductive leads and programming elements such as antifuses, for interconnecting selected leads.
- the PIC may also include, in addition, transistors and other circuit components to assist in the programming, but these transistors and other circuit components may be excluded to simplify and reduce the cost of the PIC.
- first level of conductive leads and a second level of conductive leads or just a single level of conductive leads
- any number of levels of conductive leads appropriate and compatible with the processing technology can be used.
- a first set of conductive leads and a second set of conductive leads are typically placed substantially orthogonal to each other, it should be understood that the first and second sets of leads can, if desired be oriented in a substantially different direction rather than being substantially orthogonal to each other and the invention will still be capable of being implemented.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Claims (6)
- Konstruktion, die Folgendes umfasst:ein Verdrahtungssubstrat (1001);eine Mehrzahl von Komponentenkontakten (1002-1, 1 bis 1002-6,1), die zum Aufnehmen elektronischer Komponenten über dem Verdrahtungssubstrat ausgebildet sind;eine Mehrzahl von elektrisch leitenden Bahnen (1003-1, 1 bis 1003-6,1), die über dem Verdrahtungssubstrat (1001) ausgebildet sind, wobei jede Leiterbahn mit einem entsprechenden einen der Komponentenkontakte (1002-1,1 bis 1002-6,1) elektrisch verbunden ist; undwenigstens eine programmierbare integrierte Schaltung (1005), die über einem ausgewählten Abschnitt des Verdrahtungssubstrats (1001) montiert ist, wobei die oder jede programmierbare integrierte Schaltung (1005) Folgendes beinhaltet:(a) eine Mehrzahl von elektrisch leitenden Drähten, die jeweils mit einer entsprechenden einen der Leiterbahnen (1003-1,1 bis 1003-6,1) elektrisch verbunden sind,(b) programmierbare Mittel zum selektiven elektrischen Verbinden der leitenden Drähte, um ausgewählte der Leiterbahnen programmierbar zusammenzuschalten, und(c) aktive Prüfgeräte (440-446) zum Prüfen der leitenden Drähte und/oder der Leiterbahnen (1003-1,1 bis 1003-1,6) und/oder der von den Komponentenkontakten aufgenommenen elektronischen Komponenten, wobei die aktiven Prüfgeräte Abtastmittel (440, 445) zum Abtasten von Prüfdaten umfassen, die von den elektronischen Komponenten bereitgestellt werden.
- Konstruktion nach Anspruch 1, bei der die aktiven Prüfgeräte (440-446) ferner Mittel (441-444, 446) zum Verarbeiten der abgetasteten Prüfdaten umfassen.
- Konstruktion nach Anspruch 1 oder 2, bei der wenigstens einer der leitenden Drähte in wenigstens zwei separate leitende Segmente in einer Linie miteinander unterteilt ist.
- Konstruktion nach einem der Ansprüche 1 bis 3, die ferner die von den Komponentenkontakten aufgenommenen elektronischen Komponenten beinhaltet.
- Konstruktion nach einem der Ansprüche 1 bis 4, wobei in einer der wenigstens einen programmierbaren integrierten Schaltung die Abtastmittel (440 und 445) die Aufgabe haben, ausgewählte der elektronischen Komponenten abzutasten, um die Zustände der gewählten elektronischen Komponenten zu ermitteln, und in dieser programmierbaren integrierten Schaltung die aktiven Prüfgeräte ferner Folgendes umfassen:ein erstes Mittel (441) zum Speichern von Daten, die von einem Benutzer in diese programmierbare integrierte Schaltung eingegeben wurden;Mittel (442) zum Vergleichen der Daten, die von den ausgewählten elektronischen Komponenten abgetastet wurden, mit den Daten, die in dem ersten Mittel (441) zum Speichern von Daten gespeichert sind, um zu ermitteln, ob eine Übereinstimmung zwischen den abgetasteten und den gespeicherten Daten aufgetreten ist;ein zweites Mittel (443) zum Speichern der Daten, die von den ausgewählten elektronischen Komponenten zur Verfügung stehen, als Reaktion darauf, dass eine Übereinstimmung zwischen den Daten, die in dem ersten Mittel (441) zum Speichern gespeichert sind, und den abgetasteten Daten erfasst wird; undMittel zum Ausgeben der in dem zweiten Speichermittel gespeicherten Daten zum Speichern.
- Konstruktion nach einem der Ansprüche 1 bis 5, bei der es mehrere Lagen der Leiterbahnen (1003-1,1 bis 1003-6,1) gibt.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US59841790A | 1990-10-15 | 1990-10-15 | |
US598417 | 1990-10-15 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0481703A2 EP0481703A2 (de) | 1992-04-22 |
EP0481703A3 EP0481703A3 (en) | 1992-08-05 |
EP0481703B1 true EP0481703B1 (de) | 2003-09-17 |
Family
ID=24395463
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91309424A Expired - Lifetime EP0481703B1 (de) | 1990-10-15 | 1991-10-14 | Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung |
Country Status (4)
Country | Link |
---|---|
US (6) | US5371390A (de) |
EP (1) | EP0481703B1 (de) |
JP (1) | JP3247898B2 (de) |
DE (1) | DE69133311T2 (de) |
Families Citing this family (157)
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DE69133311T2 (de) * | 1990-10-15 | 2004-06-24 | Aptix Corp., San Jose | Verbindungssubstrat mit integrierter Schaltung zur programmierbaren Verbindung und Probenuntersuchung |
US5528600A (en) | 1991-01-28 | 1996-06-18 | Actel Corporation | Testability circuits for logic arrays |
JP2960560B2 (ja) * | 1991-02-28 | 1999-10-06 | 株式会社日立製作所 | 超小型電子機器 |
EP0518701A3 (en) * | 1991-06-14 | 1993-04-21 | Aptix Corporation | Field programmable circuit module |
WO1993006559A1 (en) * | 1991-09-23 | 1993-04-01 | Aptix Corporation | Universal interconnect matrix array |
DE69324637T2 (de) | 1992-07-31 | 1999-12-30 | Hughes Electronics Corp., El Segundo | Sicherheitssystem für integrierte Schaltung und Verfahren mit implantierten Leitungen |
US5490042A (en) * | 1992-08-10 | 1996-02-06 | Environmental Research Institute Of Michigan | Programmable silicon circuit board |
JP3256603B2 (ja) * | 1993-07-05 | 2002-02-12 | 株式会社東芝 | 半導体装置及びその製造方法 |
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US5917229A (en) | 1994-02-08 | 1999-06-29 | Prolinx Labs Corporation | Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect |
US5962815A (en) | 1995-01-18 | 1999-10-05 | Prolinx Labs Corporation | Antifuse interconnect between two conducting layers of a printed circuit board |
US5783846A (en) * | 1995-09-22 | 1998-07-21 | Hughes Electronics Corporation | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
US5844297A (en) * | 1995-09-26 | 1998-12-01 | Symbios, Inc. | Antifuse device for use on a field programmable interconnect chip |
US6046600A (en) * | 1995-10-31 | 2000-04-04 | Texas Instruments Incorporated | Process of testing integrated circuit dies on a wafer |
US5969538A (en) | 1996-10-31 | 1999-10-19 | Texas Instruments Incorporated | Semiconductor wafer with interconnect between dies for testing and a process of testing |
FR2741475B1 (fr) * | 1995-11-17 | 2000-05-12 | Commissariat Energie Atomique | Procede de fabrication d'un dispositif de micro-electronique comportant sur un substrat une pluralite d'elements interconnectes |
US5757212A (en) * | 1995-12-21 | 1998-05-26 | Cypress Semiconductor Corp. | Method and apparatus for providing a pin configurable architecture for frequency synthesizers |
US5759871A (en) * | 1996-07-26 | 1998-06-02 | Advanced Micro Devices, Inc. | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
US6541709B1 (en) * | 1996-11-01 | 2003-04-01 | International Business Machines Corporation | Inherently robust repair process for thin film circuitry using uv laser |
JPH10200050A (ja) * | 1997-01-06 | 1998-07-31 | Mitsubishi Electric Corp | 半導体集積装置 |
US5821776A (en) * | 1997-01-31 | 1998-10-13 | Actel Corporation | Field programmable gate array with mask programmed analog function circuits |
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-
1991
- 1991-10-14 DE DE69133311T patent/DE69133311T2/de not_active Expired - Lifetime
- 1991-10-14 EP EP91309424A patent/EP0481703B1/de not_active Expired - Lifetime
- 1991-10-15 JP JP29508591A patent/JP3247898B2/ja not_active Expired - Lifetime
-
1992
- 1992-11-04 US US07/972,884 patent/US5371390A/en not_active Expired - Fee Related
-
1994
- 1994-09-02 US US08/300,289 patent/US5504354A/en not_active Expired - Lifetime
-
1996
- 1996-01-31 US US08/594,929 patent/US5654564A/en not_active Expired - Lifetime
-
1997
- 1997-07-17 US US08/895,718 patent/US5973340A/en not_active Expired - Lifetime
-
1999
- 1999-06-25 US US09/344,220 patent/US6160276A/en not_active Expired - Lifetime
-
2000
- 2000-12-01 US US09/728,887 patent/US20020163019A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US5504354A (en) | 1996-04-02 |
DE69133311T2 (de) | 2004-06-24 |
US5654564A (en) | 1997-08-05 |
US20020163019A1 (en) | 2002-11-07 |
DE69133311D1 (de) | 2003-10-23 |
US5371390A (en) | 1994-12-06 |
US5973340A (en) | 1999-10-26 |
EP0481703A3 (en) | 1992-08-05 |
US6160276A (en) | 2000-12-12 |
JP3247898B2 (ja) | 2002-01-21 |
EP0481703A2 (de) | 1992-04-22 |
JPH07170038A (ja) | 1995-07-04 |
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