Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/528—Geometry or layout of the interconnection structure
  • H01L23/5286—Arrangements of power or ground buses
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
  • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L24/02—Bonding areas ; Manufacturing methods related thereto
  • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
  • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/14—Integrated circuits
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance

Definitions

• the present invention pertains to integrated circuits and more particularly to the distribution of power to elements within the circuit.
• the metallization inter ⁇ connection layers become thinner and narrower.
• Such metallization is used to provide power to each of the power receiving components in the circuit and for supplying ground connections throughout the circuit.
• the circuit trace resistance becomes greater thereby increasing the heat dissipation of the integrated circuit and reducing the amplitude of the supply voltage at the circuit elements.
• the reduction in the metallization dimensions further can have an adverse affect on the inductive and capacitive parameters of the. integrated circuit.
• the present invention comprises a power distribution network for an integrated circuit which includes a first conductor pattern which is fabrica'ted to supply power to the individual elements within the integrated circuit.
• a passivation layer is fabricated to cover the circuit elements but is open over a substantial area of the first conductor pattern.
• a second conductor pattern is fabricated on the integrated circuit with a similar pattern to that of the first conductor pattern. The second conductor pattern is positioned to be in contact with the first conductor pattern through the opening in the passivation layer. The second conductive pattern is essentially connected to the first conductor pattern along its entire length.
• FIGURE 1 is a perspective view of a metallization pattern for an integrated circuit
• FIGURE 2 is a sectional view of one of the strips of the metallization pattern shown in FIGURE 1;
• FIGURE 3 is a sectional view of a metallization pattern in accordance with the present invention and;
• FIGURE 4 is a sectional view of a metallization pattern for a plurality of power distribution lines.
• FIGURE 1 A power distribution network for an integrated circuit is illustrated in FIGURE 1.
• a silicon substrate 10 serves as the base for the fabrication of integrated circuit elements on the upper surface thereof.
• a power distribution network for supplying power to the elements within the circuit.
• the network includes a first group of parallel strips 12-24 which are connected in common to a perpendicular strip 26. Strip 26 is in turn connected to a bonding pad 28.
• a second portion of the power distribution network comprises a plurality of parallel strips 30-44. These parallel strips are in turn connected to a perpendicular, common strip 46 which is itself connected to a bonding pad 48.
• a positive voltage is connected through a wire bond to the pad 28 and a negative voltage or ground is connected through a wire bond to pad 48.
• the power thus supplied is distributed to the elements of the circuit through the strips 12-24 and 30-44.
• FIGURE 2 A cross sectional view of a power distribution strip as illustrated in FIGURE 1 is shown in FIGURE 2.
• the silicon substrate 10 is fabricated to have a diffusion region 50 fabricated therein.
• the diffusion region 50 forms a part of the circuit elements within the integrated circuit fabricated on the substrate 10.
• a dielectric separation layer 51 is formed on the surface of the silicon substrate 20.
• Layer 51 is typically silicon dioxide having a thickness of 6,000- 10,000 Angstroms.
• a conductor 52 which is in oh ic contact with the diffusion region 50.
• the conductor 52 is fabricated in a pattern which is similar to that shown for the power distribution network strips in FIGURE 1.
• the conductor 52 is typically aluminum or aluminum alloy with a thickness of 6,000-12,000 Angstroms.
• a preferred method for fabricating conductor 52 is by sputtering or evaporation techniques followed by photolithographic etching.
• a passivation layer 54 is laid down over the conductor 52 and the separation layer 51.
• an opening 56 is formed in the passivation layer 54.
• the opening 56 extends along the longitudinal dimension of the conductor layer 52 but is slightly narrower than the conductor layer. The opening 56 thus has slightly less area than that of the conductor layer 52.
• the overlap of the passivation layer 54 over the edges of the conductor 52 forms a sealed junction.
• the passivation layer 54 is typically glass or silicon dioxide with a thickness of 9,000-12,000 Angstroms.
• a layer of adhesion and diffusion barrier metal 58 is formed over the opening 56 and over the adjacent edges of the passivation layer 54.
• Typical materials for use as the layer 58 include titanium, tungsten, molybdenum and chromium. These metals likewise can be deposited by means of sputtering or evaporation techniques.
• the material of layer 58 provides electrical contact and adhesion to the conductor 52, passivation layer 54 and an additional conductor layer to be added above the layer 58.
• Layer 58 also functions as a diffusion barrier. The thickness of layer 58 is typically 2000-2500 Angstroms.
• a metal conductor 60 in a configuration similar to the conductor 52.
• the conductor 60 is fabricated of aluminum, copper, gold or silver using conventional deposition and photolithographic etching.
• the typical thickness of layer 60 is 4000-6000 Angstroms.
• the adhesion and diffusion barrier layer 58 is also photolithographically configured to be similar to the conductor 52.
• the conductive layer 60 together with the conductor 58 extends longitudinally above the conductive layer 52 to essentially form a single conductive strip having an enhanced thickness. This enhanced thickness reduces the trace resistance of the power conduction lines for the integrated circuit.
• FIGURE 3 A cross sectional illustration of the pov-er distribution lines of the present invention is shown in FIGURE 3 wherein the conductor layer 52 is deposited directly on the surface of substrate 10 over separation layer 51 in the absence of a diffused region, such as 50 shown in FIGURE 2.
• the conductive layers 52 and 60, separation layer 51, adhesion and barrier layer 58 and passivation layer 52 are the same as shown for the embodiment illustrated in FIGURE 2.
• FIGURE 4 A further embodiment of the present invention is illustrated in FIGURE 4.
• a silicon substrate 54 has a dielectric separation layer 65 on the surface thereof.
• Positive and negative power distribution trace lines 66 and 68 respectively are fabricated over layer 65. These lines are fabricated of materials such as, for example, aluminum or aluminum alloy.
• the conductive lines 66 and 68 have a thickness on the order of 6000-12,000 Angstroms.
• the passivation layer 70 has a thickness of approximately 9000-12,000 Angstroms.
• an adhesion and diffusion barrier layer 76 is typically titanium, tungsten, molybdenum or chromium and has a typical thickness of 2000-2500 Angstroms.
• a metal conductor 78 which is typically aluminum, copper, gold or silver.
• Layers 76 and 78 are etched to produce a plurality of strips, one over each of the conductor lines 66 and 68. Each of the strips of layers 76 and 78 are wider .than the underlying conductive lines 66 and 68.
• a typical thickness for layer 76 is 2000-2500 Angstroms.
• a typical thickness for layer 78 is 4000-6000 Angstroms.
• Layers 76 and 78 are photolithographically etched such that they are formed into strips corresponding to each of the conductor lines 66 and 68.
• the strips of layer 78, like the strips of layer 76 are wider than the underlying conductive lines. This serves to reduce the resistance of the power distribution lines and to enhance the capacitive coupling between the power distribution lines.
• the present invention provides a power distribution network wherein additional layers of metallization are formed over the conductor lines which interconnect the active elements in an integrated circuit.
• the enhanced power distribution lines have greater thickness and optionally greater width to reduce the resistance in the power lines, reduce inductance and control power line capacitance to enhance the performance of the integrated circuit.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Geometry (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 1980
  • 1980-09-15 EP EP81901561A patent/EP0060253A1/de not_active Withdrawn
  • 1980-09-15 WO PCT/US1980/001184 patent/WO1982001102A1/en unknown

Non-Patent Citations (1)

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