GB1490715A - Methods of forming a conductive pattern on a supporting body - Google Patents
Methods of forming a conductive pattern on a supporting bodyInfo
- Publication number
- GB1490715A GB1490715A GB52864/74A GB5286474A GB1490715A GB 1490715 A GB1490715 A GB 1490715A GB 52864/74 A GB52864/74 A GB 52864/74A GB 5286474 A GB5286474 A GB 5286474A GB 1490715 A GB1490715 A GB 1490715A
- Authority
- GB
- United Kingdom
- Prior art keywords
- layer
- conductive
- auxiliary layer
- pattern
- apertures
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Vapour Deposition (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
1490715 Semiconductor devices; printed circuits PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 6 Dec 1974 [10 Dec 1973] 52864/74 Headings HlK and H1R A method of manufacturing an electrical device including a pattern of conductors on a substrate comprises providing an auxiliary layer on the substrate with apertures corresponding to part of the pattern, depositing a layer of conductive material over the auxiliary layer and apertures, selectively removing at least the upper surface of the auxiliary layer together with the part of the conductive layers on top of it, leaving a first part of the pattern of conductors, providing a second auxiliary layer on the substrate and conductive pattern and repeating the process to form a second part of the pattern. The conductor pattern may be the base and emitter metallization of a transistor and the method allows inter-conductor spacings of less than 1 micron. As shown in Fig. 5, the transistor comprises an, e.g. n-type collector zone 5, a diffuser or implanted base zone 6 having a highly doped contact zone 6A and a less highly doped zone 6B in which emitter zone 7 is formed by diffusion or implantation. Over the substrate partially coated with insulation 8, e.g. silicon oxide or nitride an auxiliary layer is deposited which preferably as shown consists of two layers 9A, 9B. Layer 9A may be Al, Cu, Mg or Ag and layer 9B Cr, Ti, Pd, Mo, W, Ta, Ni or Au. Using a photoresist mask 10, apertures are etched in the auxiliary layer in two stages. In a first stage, apertures are etched in layer 9A, and in a second apertures are etched in 9B with undercutting, layer 9B optionally functioning as the etching mask for the second stage. The assembly is coated by vapour deposition or the like with a conductive layer different from the auxiliary layer and which as shown in Fig. 1 consists of a layer 3A which adheres well to the substrate, e.g. Ti, Cr, Rh, Zr, Ta, W, Mo and a layer 3B chosen for its conductivity, e.g. Pt, Rh, Co, Mo, W. By etching away the remainder of the auxiliary layer 9A, 9B with concomitant removal of the conductive layer on top of it, a first part of the conductive pattern is left, which provides the base metallization. A second auxiliary layer, comprising layers 11A, 11B (Fig. 9) deposited as before and apertures formed therein over the emitter regions. A further conductive layer is applied by vapour deposition or the like, comprising as shown in Fig. 9 layer 4A, e.g. Ti, Cr, Rh, Zr, Ta, W, Co, Mo, layer 4B, e.g. Pt, Rh, Co or Mo and layer 4C of gold. The second auxiliary layer is now etched away with concomitant removal of the conductive layer a top of it to leave a second part of the conductive pattern providing the emitter metallization. Since this is formed separately from the base metallization it may be thicker or otherwise formed to provide for greater required current-carrying capacity. In modifications the first and second parts of the conductive pattern may partially overlap, without intervening insulation (Figs 10, 11, not shown) or with intervening insulation such as glass (Figs 12 to 14 and 18, not shown) the latter embodiment being used in forming charge coupled shift registers. In a further embodiment (Figs 15 to 17, not shown) only the top layer of a two component auxiliary layer is completely removed, the bottom layer, in this case tungsten or polycrystalline silicon forming part of the conductive pattern, in particular the collector connection. The auxiliary layer need not be metal or conductive, e.g. it may be a photoresist and an effect similar to undercutting may be achieved by applying the activating radiation at an angle.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7316851A NL7316851A (en) | 1973-12-10 | 1973-12-10 | PROCESS OF MANUFACTURING A DEVICE, IN PARTICULAR A SEMICONDUCTOR DEVICE, WITH A CONDUCTOR PATTERN ON A SUPPORT BODY, AND DEVICE MANUFACTURED BY THE PROCESS. |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1490715A true GB1490715A (en) | 1977-11-02 |
Family
ID=19820155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB52864/74A Expired GB1490715A (en) | 1973-12-10 | 1974-12-06 | Methods of forming a conductive pattern on a supporting body |
Country Status (12)
Country | Link |
---|---|
JP (1) | JPS5646263B2 (en) |
BE (1) | BE823138A (en) |
BR (1) | BR7410276A (en) |
CA (1) | CA1018677A (en) |
CH (1) | CH588164A5 (en) |
DE (1) | DE2455963A1 (en) |
ES (1) | ES432700A1 (en) |
FR (1) | FR2254105B1 (en) |
GB (1) | GB1490715A (en) |
IT (1) | IT1026859B (en) |
NL (1) | NL7316851A (en) |
SE (1) | SE405429B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112259455A (en) * | 2020-10-19 | 2021-01-22 | 扬州扬杰电子科技股份有限公司 | Method for improving metal residue of Ag surface product with passivation layer structure |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5370688A (en) * | 1976-12-06 | 1978-06-23 | Toshiba Corp | Production of semoconductor device |
CN108235597B (en) * | 2018-02-08 | 2024-02-23 | 惠州奔达电子有限公司 | PCB manufacturing method and PCB |
JP7164773B2 (en) * | 2018-03-02 | 2022-11-02 | 東京エレクトロン株式会社 | How to transfer the pattern to the layer |
-
1973
- 1973-12-10 NL NL7316851A patent/NL7316851A/en not_active Application Discontinuation
-
1974
- 1974-11-27 DE DE19742455963 patent/DE2455963A1/en not_active Withdrawn
- 1974-12-05 CA CA215,317A patent/CA1018677A/en not_active Expired
- 1974-12-06 CH CH1625474A patent/CH588164A5/xx not_active IP Right Cessation
- 1974-12-06 GB GB52864/74A patent/GB1490715A/en not_active Expired
- 1974-12-06 IT IT30285/74A patent/IT1026859B/en active
- 1974-12-07 JP JP14014074A patent/JPS5646263B2/ja not_active Expired
- 1974-12-07 ES ES432700A patent/ES432700A1/en not_active Expired
- 1974-12-09 BE BE151322A patent/BE823138A/en unknown
- 1974-12-09 SE SE7415380A patent/SE405429B/en unknown
- 1974-12-09 BR BR10276/74A patent/BR7410276A/en unknown
- 1974-12-10 FR FR7440442A patent/FR2254105B1/fr not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112259455A (en) * | 2020-10-19 | 2021-01-22 | 扬州扬杰电子科技股份有限公司 | Method for improving metal residue of Ag surface product with passivation layer structure |
CN112259455B (en) * | 2020-10-19 | 2024-01-26 | 扬州扬杰电子科技股份有限公司 | Method for improving metal residue of Ag surface product with passivation layer structure |
Also Published As
Publication number | Publication date |
---|---|
CA1018677A (en) | 1977-10-04 |
NL7316851A (en) | 1975-06-12 |
DE2455963A1 (en) | 1975-06-12 |
JPS5092089A (en) | 1975-07-23 |
JPS5646263B2 (en) | 1981-10-31 |
SE7415380L (en) | 1975-06-11 |
FR2254105B1 (en) | 1978-06-23 |
ES432700A1 (en) | 1977-03-01 |
FR2254105A1 (en) | 1975-07-04 |
SE405429B (en) | 1978-12-04 |
IT1026859B (en) | 1978-10-20 |
CH588164A5 (en) | 1977-05-31 |
BE823138A (en) | 1975-06-09 |
AU7621174A (en) | 1976-06-10 |
BR7410276A (en) | 1976-06-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |