EP0060253A1 - Integrated circuit power distribution network - Google Patents

Integrated circuit power distribution network

Info

Publication number
EP0060253A1
EP0060253A1 EP81901561A EP81901561A EP0060253A1 EP 0060253 A1 EP0060253 A1 EP 0060253A1 EP 81901561 A EP81901561 A EP 81901561A EP 81901561 A EP81901561 A EP 81901561A EP 0060253 A1 EP0060253 A1 EP 0060253A1
Authority
EP
European Patent Office
Prior art keywords
conductor pattern
passivation layer
circuit
layer
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP81901561A
Other languages
German (de)
French (fr)
Inventor
A. Mulholland; Wayne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of EP0060253A1 publication Critical patent/EP0060253A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention pertains to integrated circuits and more particularly to the distribution of power to elements within the circuit.
  • the metallization inter ⁇ connection layers become thinner and narrower.
  • Such metallization is used to provide power to each of the power receiving components in the circuit and for supplying ground connections throughout the circuit.
  • the circuit trace resistance becomes greater thereby increasing the heat dissipation of the integrated circuit and reducing the amplitude of the supply voltage at the circuit elements.
  • the reduction in the metallization dimensions further can have an adverse affect on the inductive and capacitive parameters of the. integrated circuit.
  • the present invention comprises a power distribution network for an integrated circuit which includes a first conductor pattern which is fabrica'ted to supply power to the individual elements within the integrated circuit.
  • a passivation layer is fabricated to cover the circuit elements but is open over a substantial area of the first conductor pattern.
  • a second conductor pattern is fabricated on the integrated circuit with a similar pattern to that of the first conductor pattern. The second conductor pattern is positioned to be in contact with the first conductor pattern through the opening in the passivation layer. The second conductive pattern is essentially connected to the first conductor pattern along its entire length.
  • FIGURE 1 is a perspective view of a metallization pattern for an integrated circuit
  • FIGURE 2 is a sectional view of one of the strips of the metallization pattern shown in FIGURE 1;
  • FIGURE 3 is a sectional view of a metallization pattern in accordance with the present invention and;
  • FIGURE 4 is a sectional view of a metallization pattern for a plurality of power distribution lines.
  • FIGURE 1 A power distribution network for an integrated circuit is illustrated in FIGURE 1.
  • a silicon substrate 10 serves as the base for the fabrication of integrated circuit elements on the upper surface thereof.
  • a power distribution network for supplying power to the elements within the circuit.
  • the network includes a first group of parallel strips 12-24 which are connected in common to a perpendicular strip 26. Strip 26 is in turn connected to a bonding pad 28.
  • a second portion of the power distribution network comprises a plurality of parallel strips 30-44. These parallel strips are in turn connected to a perpendicular, common strip 46 which is itself connected to a bonding pad 48.
  • a positive voltage is connected through a wire bond to the pad 28 and a negative voltage or ground is connected through a wire bond to pad 48.
  • the power thus supplied is distributed to the elements of the circuit through the strips 12-24 and 30-44.
  • FIGURE 2 A cross sectional view of a power distribution strip as illustrated in FIGURE 1 is shown in FIGURE 2.
  • the silicon substrate 10 is fabricated to have a diffusion region 50 fabricated therein.
  • the diffusion region 50 forms a part of the circuit elements within the integrated circuit fabricated on the substrate 10.
  • a dielectric separation layer 51 is formed on the surface of the silicon substrate 20.
  • Layer 51 is typically silicon dioxide having a thickness of 6,000- 10,000 Angstroms.
  • a conductor 52 which is in oh ic contact with the diffusion region 50.
  • the conductor 52 is fabricated in a pattern which is similar to that shown for the power distribution network strips in FIGURE 1.
  • the conductor 52 is typically aluminum or aluminum alloy with a thickness of 6,000-12,000 Angstroms.
  • a preferred method for fabricating conductor 52 is by sputtering or evaporation techniques followed by photolithographic etching.
  • a passivation layer 54 is laid down over the conductor 52 and the separation layer 51.
  • an opening 56 is formed in the passivation layer 54.
  • the opening 56 extends along the longitudinal dimension of the conductor layer 52 but is slightly narrower than the conductor layer. The opening 56 thus has slightly less area than that of the conductor layer 52.
  • the overlap of the passivation layer 54 over the edges of the conductor 52 forms a sealed junction.
  • the passivation layer 54 is typically glass or silicon dioxide with a thickness of 9,000-12,000 Angstroms.
  • a layer of adhesion and diffusion barrier metal 58 is formed over the opening 56 and over the adjacent edges of the passivation layer 54.
  • Typical materials for use as the layer 58 include titanium, tungsten, molybdenum and chromium. These metals likewise can be deposited by means of sputtering or evaporation techniques.
  • the material of layer 58 provides electrical contact and adhesion to the conductor 52, passivation layer 54 and an additional conductor layer to be added above the layer 58.
  • Layer 58 also functions as a diffusion barrier. The thickness of layer 58 is typically 2000-2500 Angstroms.
  • a metal conductor 60 in a configuration similar to the conductor 52.
  • the conductor 60 is fabricated of aluminum, copper, gold or silver using conventional deposition and photolithographic etching.
  • the typical thickness of layer 60 is 4000-6000 Angstroms.
  • the adhesion and diffusion barrier layer 58 is also photolithographically configured to be similar to the conductor 52.
  • the conductive layer 60 together with the conductor 58 extends longitudinally above the conductive layer 52 to essentially form a single conductive strip having an enhanced thickness. This enhanced thickness reduces the trace resistance of the power conduction lines for the integrated circuit.
  • FIGURE 3 A cross sectional illustration of the pov-er distribution lines of the present invention is shown in FIGURE 3 wherein the conductor layer 52 is deposited directly on the surface of substrate 10 over separation layer 51 in the absence of a diffused region, such as 50 shown in FIGURE 2.
  • the conductive layers 52 and 60, separation layer 51, adhesion and barrier layer 58 and passivation layer 52 are the same as shown for the embodiment illustrated in FIGURE 2.
  • FIGURE 4 A further embodiment of the present invention is illustrated in FIGURE 4.
  • a silicon substrate 54 has a dielectric separation layer 65 on the surface thereof.
  • Positive and negative power distribution trace lines 66 and 68 respectively are fabricated over layer 65. These lines are fabricated of materials such as, for example, aluminum or aluminum alloy.
  • the conductive lines 66 and 68 have a thickness on the order of 6000-12,000 Angstroms.
  • the passivation layer 70 has a thickness of approximately 9000-12,000 Angstroms.
  • an adhesion and diffusion barrier layer 76 is typically titanium, tungsten, molybdenum or chromium and has a typical thickness of 2000-2500 Angstroms.
  • a metal conductor 78 which is typically aluminum, copper, gold or silver.
  • Layers 76 and 78 are etched to produce a plurality of strips, one over each of the conductor lines 66 and 68. Each of the strips of layers 76 and 78 are wider .than the underlying conductive lines 66 and 68.
  • a typical thickness for layer 76 is 2000-2500 Angstroms.
  • a typical thickness for layer 78 is 4000-6000 Angstroms.
  • Layers 76 and 78 are photolithographically etched such that they are formed into strips corresponding to each of the conductor lines 66 and 68.
  • the strips of layer 78, like the strips of layer 76 are wider than the underlying conductive lines. This serves to reduce the resistance of the power distribution lines and to enhance the capacitive coupling between the power distribution lines.
  • the present invention provides a power distribution network wherein additional layers of metallization are formed over the conductor lines which interconnect the active elements in an integrated circuit.
  • the enhanced power distribution lines have greater thickness and optionally greater width to reduce the resistance in the power lines, reduce inductance and control power line capacitance to enhance the performance of the integrated circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Un reseau de distribution de puissance pour un circuit integre est fabrique avec le circuit sur un substrat de silicium (10). Le substrat de silicium (10) est fabrique pour former des regions de diffusion (50) faisant partie des dispositifs actifs du circuit integre. Une couche de separation dielectrique (51) est fabriquee sur la surface du substrat (10). Au-dessus de la region (50) une ligne de distribution de puissance (52) est prevue consistant en une metallisation d'aluminium ou un materiau en alliage d'aluminium. Une couche de passivation (54) est formee sur la couche dielectrique (51) et le conducteur (52) mais est ouverte au-dessus de la region centrale du conducteur (52). Une couche barriere d'adhesion et de diffusion (58) est fabriquee sur le conducteur (52) et sur la couche de passivation (54). Au-dessus de la couche (58) on depose une couche epaisse de metallisation (60) sous la forme d'une bande conductrice ayant une configuration semblable a celle de la couche conductrice sous-jacente (52). Les couches conductrices (58, 60) sont attaquees chimiquement pour avoir essentiellement la meme largeur que la ligne conductrice (52). Les couches conductrices (58 et60) peuvent eventuellement avoir une largeur plus grande que la couche sous-jacente comme cela est illustre par les couches conductrices (76 78).A power distribution network for an integrated circuit is fabricated with the circuit on a silicon substrate (10). The silicon substrate (10) is fabricated to form diffusion regions (50) which are part of the active devices of the integrated circuit. A dielectric separation layer (51) is made on the surface of the substrate (10). Above the region (50) a power distribution line (52) is provided consisting of an aluminum metallization or an aluminum alloy material. A passivation layer (54) is formed on the dielectric layer (51) and the conductor (52) but is open above the central region of the conductor (52). An adhesion and diffusion barrier layer (58) is fabricated on the conductor (52) and on the passivation layer (54). Above the layer (58) a thick layer of metallization (60) is deposited in the form of a conductive strip having a configuration similar to that of the underlying conductive layer (52). The conductive layers (58, 60) are attacked chemically to have essentially the same width as the conductive line (52). The conductive layers (58 and 60) may optionally be wider than the underlying layer as illustrated by the conductive layers (76 78).

Description

INTEGRATED CIRCUIT POWER DISTRIBUTION NETWORK
TECHNICAL FIELD
The present invention pertains to integrated circuits and more particularly to the distribution of power to elements within the circuit.
OMPI BACKGROUND ART
As integrated circuit features become smaller to achieve increased density, the metallization inter¬ connection layers become thinner and narrower. Such metallization is used to provide power to each of the power receiving components in the circuit and for supplying ground connections throughout the circuit. As the dimensions of the metallization become smaller the circuit trace resistance becomes greater thereby increasing the heat dissipation of the integrated circuit and reducing the amplitude of the supply voltage at the circuit elements. The reduction in the metallization dimensions further can have an adverse affect on the inductive and capacitive parameters of the. integrated circuit.
Therefore there exists a need for thicker and more massive metallization patterns which overcome the problems of thin patterns but do not interfere with the reduction of integrated circuit dimensions to increase circuit density.
DISCLOSURE OF THE INVENTION
The present invention comprises a power distribution network for an integrated circuit which includes a first conductor pattern which is fabrica'ted to supply power to the individual elements within the integrated circuit. A passivation layer is fabricated to cover the circuit elements but is open over a substantial area of the first conductor pattern. A second conductor pattern is fabricated on the integrated circuit with a similar pattern to that of the first conductor pattern. The second conductor pattern is positioned to be in contact with the first conductor pattern through the opening in the passivation layer. The second conductive pattern is essentially connected to the first conductor pattern along its entire length.
OMPI BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made* to the following Description taken in conjunction with the accompanying Drawings in which:
FIGURE 1 is a perspective view of a metallization pattern for an integrated circuit;
FIGURE 2 is a sectional view of one of the strips of the metallization pattern shown in FIGURE 1; FIGURE 3 is a sectional view of a metallization pattern in accordance with the present invention and;
FIGURE 4 is a sectional view of a metallization pattern for a plurality of power distribution lines.
DISCLOSURE OF THE INVENTION
A power distribution network for an integrated circuit is illustrated in FIGURE 1. A silicon substrate 10 serves as the base for the fabrication of integrated circuit elements on the upper surface thereof. As a part of the circuit fabrication process there is laid down a power distribution network for supplying power to the elements within the circuit. The network includes a first group of parallel strips 12-24 which are connected in common to a perpendicular strip 26. Strip 26 is in turn connected to a bonding pad 28.
A second portion of the power distribution network comprises a plurality of parallel strips 30-44. These parallel strips are in turn connected to a perpendicular, common strip 46 which is itself connected to a bonding pad 48.
In a typical application a positive voltage is connected through a wire bond to the pad 28 and a negative voltage or ground is connected through a wire bond to pad 48. The power thus supplied is distributed to the elements of the circuit through the strips 12-24 and 30-44.
The strips 12-24 and 30-40 are representative of power distribution strips and a substantial number of such strips are used in large scale integration. A cross sectional view of a power distribution strip as illustrated in FIGURE 1 is shown in FIGURE 2. In a typical application the silicon substrate 10 is fabricated to have a diffusion region 50 fabricated therein. The diffusion region 50 forms a part of the circuit elements within the integrated circuit fabricated on the substrate 10. A dielectric separation layer 51 is formed on the surface of the silicon substrate 20. Layer 51 is typically silicon dioxide having a thickness of 6,000- 10,000 Angstroms. Immediately above the diffusion region 50 there is fabricated a conductor 52 which is in oh ic contact with the diffusion region 50. The conductor 52 is fabricated in a pattern which is similar to that shown for the power distribution network strips in FIGURE 1. The conductor 52 is typically aluminum or aluminum alloy with a thickness of 6,000-12,000 Angstroms. A preferred method for fabricating conductor 52 is by sputtering or evaporation techniques followed by photolithographic etching.
After the conductor layer 52 has been formed, a passivation layer 54 is laid down over the conductor 52 and the separation layer 51. By means of photolitho¬ graphic etching an opening 56 is formed in the passivation layer 54. The opening 56 extends along the longitudinal dimension of the conductor layer 52 but is slightly narrower than the conductor layer. The opening 56 thus has slightly less area than that of the conductor layer 52. The overlap of the passivation layer 54 over the edges of the conductor 52 forms a sealed junction. The passivation layer 54 is typically glass or silicon dioxide with a thickness of 9,000-12,000 Angstroms.
After the opening 56 has been formed in the passivation layer, a layer of adhesion and diffusion barrier metal 58 is formed over the opening 56 and over the adjacent edges of the passivation layer 54. Typical materials for use as the layer 58 include titanium, tungsten, molybdenum and chromium. These metals likewise can be deposited by means of sputtering or evaporation techniques. The material of layer 58 provides electrical contact and adhesion to the conductor 52, passivation layer 54 and an additional conductor layer to be added above the layer 58. Layer 58 also functions as a diffusion barrier. The thickness of layer 58 is typically 2000-2500 Angstroms. Over the adhesion and diffusion barrier layer 58 there is fabricated a metal conductor 60 in a configuration similar to the conductor 52. The conductor 60 is fabricated of aluminum, copper, gold or silver using conventional deposition and photolithographic etching. The typical thickness of layer 60 is 4000-6000 Angstroms. During photolithographic etching cf metal conductor 60, the adhesion and diffusion barrier layer 58 is also photolithographically configured to be similar to the conductor 52.
The conductive layer 60 together with the conductor 58 extends longitudinally above the conductive layer 52 to essentially form a single conductive strip having an enhanced thickness. This enhanced thickness reduces the trace resistance of the power conduction lines for the integrated circuit.
A cross sectional illustration of the pov-er distribution lines of the present invention is shown in FIGURE 3 wherein the conductor layer 52 is deposited directly on the surface of substrate 10 over separation layer 51 in the absence of a diffused region, such as 50 shown in FIGURE 2. The conductive layers 52 and 60, separation layer 51, adhesion and barrier layer 58 and passivation layer 52 are the same as shown for the embodiment illustrated in FIGURE 2.
A further embodiment of the present invention is illustrated in FIGURE 4. A silicon substrate 54 has a dielectric separation layer 65 on the surface thereof. Positive and negative power distribution trace lines 66 and 68 respectively are fabricated over layer 65. These lines are fabricated of materials such as, for example, aluminum or aluminum alloy. The conductive lines 66 and 68 have a thickness on the order of 6000-12,000 Angstroms. After the lines 66 and 68 have been formed on the substrate 64 over layer 65 there is laid down a passivation layer 70 over the upper surface of layer 65 and the conductive lines. By photolithograph and etching techniques there is created an opening 72 in the passiva¬ tion layer 70 over trace 66 and an opening 74 in a passivation layer 70 over conductive line 68. The passivation layer 70 has a thickness of approximately 9000-12,000 Angstroms. Above the passivation layer 70 and the exposed areas of conductor lines 66 and 68 there is fabricated an adhesion and diffusion barrier layer 76. This layer is typically titanium, tungsten, molybdenum or chromium and has a typical thickness of 2000-2500 Angstroms. Over the adhesion and diffusion barrier layer 76 there is fabricated a metal conductor 78 which is typically aluminum, copper, gold or silver. Layers 76 and 78 are etched to produce a plurality of strips, one over each of the conductor lines 66 and 68. Each of the strips of layers 76 and 78 are wider .than the underlying conductive lines 66 and 68. A typical thickness for layer 76 is 2000-2500 Angstroms. A typical thickness for layer 78 is 4000-6000 Angstroms.
Layers 76 and 78 are photolithographically etched such that they are formed into strips corresponding to each of the conductor lines 66 and 68. The strips of layer 78, like the strips of layer 76 are wider than the underlying conductive lines. This serves to reduce the resistance of the power distribution lines and to enhance the capacitive coupling between the power distribution lines.
In summary, the present invention provides a power distribution network wherein additional layers of metallization are formed over the conductor lines which interconnect the active elements in an integrated circuit. The enhanced power distribution lines have greater thickness and optionally greater width to reduce the resistance in the power lines, reduce inductance and control power line capacitance to enhance the performance of the integrated circuit.
Although several embodiments of the invention have been illustrated in the accompanying drawings and described in the foregoing detailed description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the scope of the invention.
OMPI

Claims

1. A power distribution network for an integrated circuit, comprising: a first conductor pattern fabricated to supply power to elements within said circuit, a passivation layer covering said circuit but open over a substantial portion of said first conductor pattern, and a second conductor pattern configured similar to said first conductor pattern and contacting said first conductor pattern through the opening in said passivation layer.
11 2. A power distribution network for an integrated circuit, comprising: a first conductor pattern fabricated in connection with power receiving elements within said circuit, said first pattern comprising a plurality of narrow, elongate strips connected in common, a passivation layer covering said circuit but exposing the central, longitudinal portions of said strips of said first pattern, and a second conductor pattern comprising a plurality of narrow, elongate strips covering the exposed portions of said first conductor pattern and bonded thereto, said second pattern connected to a bonding pad for receiving power for said circuit.
3. The power distribution network recited in Claim
2 wherein said passivation layer overlaps the longitudinal edges of said strips of said first conductor pattern.
4. The power distribution network recited in Claim 2 wherein said strips for said first and said second conductor patterns have essentially the same width.
5. The power distribution network recited in Claim 4 wherein the opening in said passivation layer, which exposes said first conductor pattern, is narrower than the strips for said first and second conductor patterns.
6. A method for producing a power distribution network for an integrated circuit, comprising the steps of: fabricating a first conductor pattern on said integrated circuit to interconnect the power receiving elements in said circuit, applying a passivation layer over said circuit and said first conductor pattern, opening the passivation layer above the first conductor pattern, and applying a second conductor pattern having a similar configuration to said first conductor pattern and connected thereto through the opening in said passivation layer.
7. A method for producing a power distribution network for an integrated circuit, comprising the steps of: fabricating a first conductor pattern on said integrated circuit to interconnect the power receiving elements in said circuit, said first conductor pattern comprising a plurality of narrow metallization strips, applying a passivation layer over said circuit and said first conductor pattern, opening said passivation layer above central, longitudinal portions of each of the strips of said first conductor pattern, and fabricating a second conductor pattern having a similar configuration as said first conductor pattern, said second pattern located on said passivation layer and extending through the opening therein to contact the strips of said first conductor pattern.
OMPI
EP81901561A 1980-09-15 1980-09-15 Integrated circuit power distribution network Withdrawn EP0060253A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1980/001184 WO1982001102A1 (en) 1980-09-15 1980-09-15 Integrated circuit power distribution network

Publications (1)

Publication Number Publication Date
EP0060253A1 true EP0060253A1 (en) 1982-09-22

Family

ID=22154534

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81901561A Withdrawn EP0060253A1 (en) 1980-09-15 1980-09-15 Integrated circuit power distribution network

Country Status (2)

Country Link
EP (1) EP0060253A1 (en)
WO (1) WO1982001102A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900000167B1 (en) * 1984-03-29 1990-01-23 산요덴끼 가부시기가이샤 Semiconductor integrated circuit having multi-layer wiring
IT1213261B (en) * 1984-12-20 1989-12-14 Sgs Thomson Microelectronics SEMICONDUCTOR DEVICE WITH METALLISATION WITH MORE THICKNESS AND PROCEDURE FOR ITS MANUFACTURE.
EP0195716B1 (en) * 1985-03-19 1992-03-25 Fairchild Semiconductor Corporation Thick bus metallization interconnect structure to reduce bus area
US5111276A (en) * 1985-03-19 1992-05-05 National Semiconductor Corp. Thick bus metallization interconnect structure to reduce bus area
JPS63312613A (en) * 1987-06-15 1988-12-21 Nec Corp Single plate capacitor
JPH0290651A (en) * 1988-09-28 1990-03-30 Nec Corp Semiconductor integrated circuit
EP0567937A3 (en) * 1992-04-30 1993-12-08 Texas Instruments Incorporated High reliability die processing
EP0646959B1 (en) * 1993-09-30 2001-08-16 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno Metallization and bonding process for manufacturing power semiconductor devices
US7339110B1 (en) 2003-04-10 2008-03-04 Sunpower Corporation Solar cell and method of manufacture
US7388147B2 (en) * 2003-04-10 2008-06-17 Sunpower Corporation Metal contact structure for solar cell and method of manufacture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3809625A (en) * 1972-08-15 1974-05-07 Gen Motors Corp Method of making contact bumps on flip-chips
US4113578A (en) * 1973-05-31 1978-09-12 Honeywell Inc. Microcircuit device metallization
DE2428373C2 (en) * 1974-06-12 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Method for the production of solderable connection contacts on a semiconductor arrangement
US3918032A (en) * 1974-12-05 1975-11-04 Us Army Amorphous semiconductor switch and memory with a crystallization-accelerating layer
US4042954A (en) * 1975-05-19 1977-08-16 National Semiconductor Corporation Method for forming gang bonding bumps on integrated circuit semiconductor devices
US4176443A (en) * 1977-03-08 1979-12-04 Sgs-Ates Componenti Elettronici S.P.A. Method of connecting semiconductor structure to external circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8201102A1 *

Also Published As

Publication number Publication date
WO1982001102A1 (en) 1982-04-01

Similar Documents

Publication Publication Date Title
US6144100A (en) Integrated circuit with bonding layer over active circuitry
JP2773578B2 (en) Method for manufacturing semiconductor device
US4687552A (en) Rhodium capped gold IC metallization
US7329562B2 (en) Process of producing semiconductor chip with surface interconnection at bump
US5418186A (en) Method for manufacturing a bump on a semiconductor chip
US3751292A (en) Multilayer metallization system
US7880300B2 (en) Semiconductor chip comprising a metal coating structure and associated production method
RU97107096A (en) METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
KR910014996A (en) Integrated Circuit Solder Die-Adhesive Design and Methods
GB2151079A (en) Semiconductor device structures
EP0060253A1 (en) Integrated circuit power distribution network
US3968360A (en) High resolution photoconductive array and process for fabricating same
KR20010033664A (en) A single step electroplating process for interconnect via fill and metal line patterning
JPS6329961A (en) Manufacture of thin film passive circuit with resistance line which has different layer resistance and the passive circuit manufactured
WO2018219101A1 (en) Back metal capacitor structure of compound semiconductor and manufacturing method therefor
JPS61114585A (en) Electric connection structure and formation thereof
JPH06105708B2 (en) Semiconductor device
JPH09260645A (en) Semiconductor device
US3408271A (en) Electrolytic plating of metal bump contacts to semiconductor devices upon nonconductive substrates
US3442012A (en) Method of forming a flip-chip integrated circuit
KR20000047626A (en) Process for manufacturing semiconductor device
US7005360B2 (en) Method for fabricating a microelectronic circuit including applying metal over and thickening the integrated coil to increase conductivity
JPH03101233A (en) Electrode structure and its manufacture
GB1490715A (en) Methods of forming a conductive pattern on a supporting body
JPH02198141A (en) Manufacture of bump electrode of semiconductor device

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT CH DE FR GB LU NL SE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19821115

RIN1 Information on inventor provided before grant (corrected)

Inventor name: MULHOLLAND; WAYNE, A.