EP0000545B1 - Procédé de fabrication d'un dispositif semiconducteur à auto-alignement - Google Patents
Procédé de fabrication d'un dispositif semiconducteur à auto-alignement Download PDFInfo
- Publication number
- EP0000545B1 EP0000545B1 EP78100443A EP78100443A EP0000545B1 EP 0000545 B1 EP0000545 B1 EP 0000545B1 EP 78100443 A EP78100443 A EP 78100443A EP 78100443 A EP78100443 A EP 78100443A EP 0000545 B1 EP0000545 B1 EP 0000545B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- regions
- semiconductor body
- accordance
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title claims description 29
- 239000010410 layer Substances 0.000 claims description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 230000000873 masking effect Effects 0.000 claims description 16
- 230000005669 field effect Effects 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000001465 metallisation Methods 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 2
- 238000010884 ion-beam technique Methods 0.000 claims 2
- 238000002955 isolation Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000035515 penetration Effects 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
Definitions
- the invention relates to a method for producing a semiconductor arrangement of the type specified in the preamble of patent claim 1.
- a preferred field of application for this method is the production of insulating layer field-effect transistor structures which are equipped with so-called self-aligned gate electrodes.
- Such field effect transistors with a self-aligned gate are already known per se.
- the associated conventional manufacturing processes use a mask made of a high temperature resistant material for masking during the formation of the source and drain regions, i.e. a material capable of withstanding high temperatures on the order of 1000 ° C and higher.
- This masking layer can be made of silicon, for example, as described for the processes described in US Pat. Nos. 3,475,234 and 3,544,399, using polycrystalline silicon as the masking material that remains in the gate region for the final formation of the gate electrode. Since such structures are insulating layer field effect transistors, a layer of an insulating material, e.g. of silicon dioxide, under the silicon-containing masking layer.
- the high temperature resistant material itself may already be an insulating material, e.g. Silicon nitride, which remains as a gate dielectric in the gate area.
- the high-temperature resistant material e.g. Silicon nitride or a double layer of silicon nitride over silicon dioxide, for edge definition of the source and drain regions adjoining the gate region; it remains as a thin gate dielectric in the final field effect transistor structure.
- a thick oxide layer is thermally grown over the source and drain, the silicon nitride layer present in the gate region serving as an oxidation-inhibiting mask to prevent the thin gate insulating layer from increasing in thickness.
- a conductive gate electrode is formed in the gate area, the thin silicon nitride layer or, after its removal, another thin insulating layer also serving to delimit the area provided as the gate area.
- the main advance in such a self-aligned gate structure has been that it has improved the positioning of the gate electrode and gate insulating layer relative to the source and drain regions.
- the gate electrode had to be made larger relative to the channel length effective between the source and drain, i.e. there was a significant overlap between the gate electrode and the source and drain regions. This resulted in undesired stray capacitances in the form of gate overlap capacitances, which led to a deterioration in the frequency properties or the switching speed of such field-effect transistor components in integrated circuits.
- the dopants can first be introduced by diffusion or ion implantation in such a way that very flat surface areas of the appropriate conductivity type form, which is followed by a so-called driving-in step to be carried out at high temperatures, through which the source and drain are driven deeper into the semiconductor body.
- driving-in step to be carried out at high temperatures, through which the source and drain are driven deeper into the semiconductor body.
- the doping atoms migrate to a certain extent below the gate masking layer. As a result, there was nevertheless an overlap of the gate with the source and drain and the resulting disadvantageous consequences.
- the layer wi is considerably lower resistances in the order of 8 to 10 ⁇ / ⁇ are required.
- source and drain regions with such a low sheet resistance were produced by one of the diffusion methods described above for forming the source and drain regions with a depth extension in the substrate in the order of magnitude of 1000 nm.
- the invention achieves the object of specifying a method for producing a semiconductor arrangement, in particular an insulating layer field-effect transistor structure, which is improved with respect to the overlap-free self-adjustment of doping regions relative to a surface layer, in which the overlap-free self-adjustment also occurs at a relatively deep in doping regions reaching the semiconductor body can be achieved.
- buried areas completely enclosed by the material of the semiconductor body are first formed in the mutual arrangement defined by the masking layer on the semiconductor surface by means of ion implantation, whereupon a subsequent heat treatment brings about a targeted expansion of the dopants present in the buried areas until the semiconductor surface is reached.
- the channel region is always exactly and completely covered by the gate electrode, but on the other hand that there is no gate overlap with the source and drain regions formed in this way.
- FIG. 1 shows a semiconductor body or a substrate 10 of the P conductivity type, the specific resistance value of which is approximately 0.1 to 1 ⁇ cm and on which an approximately 900 nm thick silicon dioxide layer 11 is formed.
- This layer 11 can be formed in a conventional manner by thermal oxidation or otherwise deposited, e.g. by vapor deposition or sputtering.
- An opening 12 is produced in layer 11 using conventional photoiitography and etching methods, so that the structure shown in FIG. 1 results.
- a thin layer 13 of silicon dioxide with a thickness of approximately 50 nm is then allowed to grow in the area of the opening 12, preferably thermally.
- a silicon layer 14 is applied over this by means of conventional methods for depositing silicon, for example described in US Pat. No. 3,424,629. This process step is carried out at a temperature on the order of 500 to 900 ° C and usually at atmospheric pressure.
- the silicon layer 14 is a polycrystalline structure since it is formed on the silicon dioxide layers 11 and 13.
- the thickness of the layer 14 is approximately 900 nm.
- an approximately 80 nm thick silicon dioxide layer 15 is produced in a conventional manner per se, but preferably by thermal oxidation of a part of the surface of the silicon layer 14.
- the regions 18 and 19 buried in the semiconductor body 10 are then formed by means of ion implantation in accordance with FIG. 4.
- N-type dopants for example phosphorus
- the implantation step can be carried out either directly through the unmasked, relatively thin silicon dioxide layer 13 or, as shown in FIG. 4, after the silicon dioxide layer 13 not covered by the silicon layer 14 'has been removed beforehand. 4, the silicon dioxide layer arranged below the mask in the form of the silicon layer 14 'is designated by 13'.
- a conventional etching process for example under Buffered hydrofluoric acid can be used.
- the silicon dioxide layer 15 will also be removed, while the layer 11, which is considerably thicker in comparison, remains essentially unchanged.
- the ion implantation must be carried out with sufficient radiation dosage and energy that the buried regions 18 and 19 have a concentration distribution which takes account of the following aspects.
- the same heat treatment is intended to ensure that regions 18 and 19 also move upwards expand in the direction of the surface of the semiconductor body 10 so that they just adjoin the silicon gate electrode laterally on the semiconductor surface.
- FIG. 8A shows the concentration distribution of the N-doping impurities for the regions 18 and 19 along the section line 8A-8A indicated in FIG. 4.
- regions 18 and 19 were originally created as regions completely enclosed in P-type semiconductor body 10, with a peak concentration being approximately at a distance of 0.5 ⁇ m from the semiconductor surface.
- the implantation step that can be used to form these areas 18 and 19 with the concentration profile shown can be carried out using conventional devices and methods, such as are described, for example, in US Pat. No. 3,756,862. For example, taking type 3 'P + ions, an energy value of 400 keV and a dosage of approximately 10 16 ions / cm 2 is appropriate.
- the implantation also forms a dopant distribution similar to the shape shown in FIG. 8A in the silicon layer region 14 ′. As a result, the layer 14 'is desirably provided with a low sheet resistance.
- a so-called diffusion or driving-in step is carried out at a temperature of about 950 ° C in a conventional oxidizing atmosphere, such as e.g. Steam is performed to bring the source and drain regions 18 and 19 into the form shown in FIG. 5.
- a conventional oxidizing atmosphere such as e.g. Steam
- the final dopant distribution for the source and drain regions 18 and 19 along the section line 8B-8B shown in FIG. 5 is shown in FIG. 8B.
- a silicon dioxide layer 40 is formed over the semiconductor body 10 as well as over the polycrystalline silicon gate electrode 14 '.
- the source and drain region edges next to it due to the subsequent diffusion or heat treatment step their downward expansion to the same extent can also be extended upwards so that their intersections 22 and 23 (in FIG. 5) are practically exactly aligned with the corresponding edges 24 and 25 of the silicon gate electrode 14 'with regard to their lateral adjustment.
- the preliminary ion implantation step according to FIG.
- openings 31, 32 and 28 are then produced in the silicon dioxide layer 40 as contact openings for source, drain and the gate electrode.
- the source and drain regions have a relatively low surface concentration of phosphorus. It is therefore advantageous to carry out a flat implantation of the dopants which cause the N-conduction type, for example phosphorus, in each of these contact openings, the regions designated 29, 30 and 34 being formed in FIG. 6. These areas have a high surface concentration of the N conductivity type in the order of 10 21 atoms / cm 3 , cf. in addition the concentration profile shown in FIG. 8C for the relationships shown in FIG. 6, and in particular the point 33 in FIG. 8C.
- N + conductive connection regions 29, 30 and 34 can be produced in a conventional manner by introducing dopants. However, it is preferable to fabricate these areas by implanting N-type ions, eg phosphorus, using the method described above with an energy of approximately 40 keV and a dosage of approximately 10 11 ions / cm 2 . In the last method step, as shown in FIG. 7, is carried out in a conventional manner the contact and connection metallization in the form of the connections 35, 36 and 37 for source, drain and the silicon gate. This metallization can be completely conventional in the manner customary in such integrated FET circuits, for example made of aluminum.
- N-type ions eg phosphorus
- the invention is not restricted to this but can also be applied to other self-aligned gate designs.
- the masking layer required to ensure the self-alignment of the thin gate insulating layer consists of a material that does not melt or decompose in any other way at the diffusion temperatures of the order of 1000 ° C. or greater that are used.
- Such other possibilities include, for example, self-aligned field effect transistors with silicon nitride gate technology, in which a thin layer of silicon nitride is used for the self-aligned formation of the source and drain regions relative to the thin gate insulating layer.
- metals such as molybdenum, tungsten or tantalum which are resistant to high temperatures can be used instead of the silicon described in the present exemplary embodiment in the context of such a method.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/820,991 US4128439A (en) | 1977-08-01 | 1977-08-01 | Method for forming self-aligned field effect device by ion implantation and outdiffusion |
US820991 | 1977-08-01 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0000545A1 EP0000545A1 (fr) | 1979-02-07 |
EP0000545B1 true EP0000545B1 (fr) | 1981-02-11 |
Family
ID=25232219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP78100443A Expired EP0000545B1 (fr) | 1977-08-01 | 1978-07-19 | Procédé de fabrication d'un dispositif semiconducteur à auto-alignement |
Country Status (6)
Country | Link |
---|---|
US (1) | US4128439A (fr) |
EP (1) | EP0000545B1 (fr) |
JP (1) | JPS6046831B2 (fr) |
CA (1) | CA1112374A (fr) |
DE (1) | DE2860467D1 (fr) |
IT (1) | IT1108994B (fr) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4218267A (en) * | 1979-04-23 | 1980-08-19 | Rockwell International Corporation | Microelectronic fabrication method minimizing threshold voltage variation |
JPS55151349A (en) * | 1979-05-15 | 1980-11-25 | Matsushita Electronics Corp | Forming method of insulation isolating region |
US4338616A (en) * | 1980-02-19 | 1982-07-06 | Xerox Corporation | Self-aligned Schottky metal semi-conductor field effect transistor with buried source and drain |
US4391651A (en) * | 1981-10-15 | 1983-07-05 | The United States Of America As Represented By The Secretary Of The Navy | Method of forming a hyperabrupt interface in a GaAs substrate |
JPS58170067A (ja) * | 1982-03-31 | 1983-10-06 | Fujitsu Ltd | 薄膜トランジスタの製造方法 |
NL188923C (nl) * | 1983-07-05 | 1992-11-02 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
US4648175A (en) * | 1985-06-12 | 1987-03-10 | Ncr Corporation | Use of selectively deposited tungsten for contact formation and shunting metallization |
US4734752A (en) * | 1985-09-27 | 1988-03-29 | Advanced Micro Devices, Inc. | Electrostatic discharge protection device for CMOS integrated circuit outputs |
EP0248988B1 (fr) * | 1986-06-10 | 1990-10-31 | Siemens Aktiengesellschaft | Procédé pour fabriquer des circuits à transistors complémentaires à effet de champ du type MOS à haute intégration |
US5602403A (en) * | 1991-03-01 | 1997-02-11 | The United States Of America As Represented By The Secretary Of The Navy | Ion Implantation buried gate insulator field effect transistor |
JPH05283710A (ja) * | 1991-12-06 | 1993-10-29 | Intel Corp | 高電圧mosトランジスタ及びその製造方法 |
KR0166101B1 (ko) * | 1993-10-21 | 1999-01-15 | 김주용 | 정전방전 보호회로의 트랜지스터 및 그 제조방법 |
JPH0955496A (ja) * | 1995-08-17 | 1997-02-25 | Oki Electric Ind Co Ltd | 高耐圧mosトランジスタ及びその製造方法 |
EP1050562A1 (fr) * | 1999-05-04 | 2000-11-08 | Fina Research S.A. | Composition à faible teneur en aromatiques |
KR100640207B1 (ko) * | 1999-10-29 | 2006-10-31 | 엘지.필립스 엘시디 주식회사 | 박막트랜지스터 및 그 제조방법 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3449643A (en) * | 1966-09-09 | 1969-06-10 | Hitachi Ltd | Semiconductor integrated circuit device |
BE758683A (fr) * | 1969-11-10 | 1971-05-10 | Ibm | Procede de fabrication d'un dispositif monolithique auto-isolant et structure de transistor a socle |
US3734787A (en) * | 1970-01-09 | 1973-05-22 | Ibm | Fabrication of diffused junction capacitor by simultaneous outdiffusion |
JPS4936514B1 (fr) * | 1970-05-13 | 1974-10-01 | ||
US4058887A (en) * | 1971-02-19 | 1977-11-22 | Ibm Corporation | Method for forming a transistor comprising layers of silicon dioxide and silicon nitride |
US4032372A (en) * | 1971-04-28 | 1977-06-28 | International Business Machines Corporation | Epitaxial outdiffusion technique for integrated bipolar and field effect transistors |
JPS5636585B2 (fr) * | 1973-07-02 | 1981-08-25 | ||
FR2257998B1 (fr) * | 1974-01-10 | 1976-11-26 | Commissariat Energie Atomique | |
US3899373A (en) * | 1974-05-20 | 1975-08-12 | Ibm | Method for forming a field effect device |
US4001048A (en) * | 1974-06-26 | 1977-01-04 | Signetics Corporation | Method of making metal oxide semiconductor structures using ion implantation |
US3948694A (en) * | 1975-04-30 | 1976-04-06 | Motorola, Inc. | Self-aligned method for integrated circuit manufacture |
DE2554426C3 (de) * | 1975-12-03 | 1979-06-21 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Erzeugung einer lokal hohen inversen Stromverstärkung bei einem Planartransistor sowie nach diesem Verfahren hergestellter invers betriebener Transistor |
JPS52135685A (en) * | 1976-05-10 | 1977-11-12 | Nec Corp | Semiconductor device |
US4046606A (en) * | 1976-05-10 | 1977-09-06 | Rca Corporation | Simultaneous location of areas having different conductivities |
JPS52156576A (en) * | 1976-06-23 | 1977-12-27 | Hitachi Ltd | Production of mis semiconductor device |
US4029522A (en) * | 1976-06-30 | 1977-06-14 | International Business Machines Corporation | Method to fabricate ion-implanted layers with abrupt edges to reduce the parasitic resistance of Schottky barrier fets and bipolar transistors |
-
1977
- 1977-08-01 US US05/820,991 patent/US4128439A/en not_active Expired - Lifetime
-
1978
- 1978-07-07 JP JP53082175A patent/JPS6046831B2/ja not_active Expired
- 1978-07-10 CA CA307,067A patent/CA1112374A/fr not_active Expired
- 1978-07-19 DE DE7878100443T patent/DE2860467D1/de not_active Expired
- 1978-07-19 EP EP78100443A patent/EP0000545B1/fr not_active Expired
- 1978-07-26 IT IT26098/78A patent/IT1108994B/it active
Also Published As
Publication number | Publication date |
---|---|
JPS5427376A (en) | 1979-03-01 |
DE2860467D1 (en) | 1981-03-26 |
EP0000545A1 (fr) | 1979-02-07 |
JPS6046831B2 (ja) | 1985-10-18 |
CA1112374A (fr) | 1981-11-10 |
IT7826098A0 (it) | 1978-07-26 |
IT1108994B (it) | 1985-12-16 |
US4128439A (en) | 1978-12-05 |
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