EP0000545B1 - Method for forming a semiconducter device with self-alignment - Google Patents

Description

The invention relates to a method for producing a semiconductor arrangement of the type specified in the preamble of patent claim 1. A preferred field of application for this method is the production of insulating layer field-effect transistor structures which are equipped with so-called self-aligned gate electrodes.

Such field effect transistors with a self-aligned gate are already known per se. The associated conventional manufacturing processes use a mask made of a high temperature resistant material for masking during the formation of the source and drain regions, i.e. a material capable of withstanding high temperatures on the order of 1000 ° C and higher. This masking layer can be made of silicon, for example, as described for the processes described in US Pat. Nos. 3,475,234 and 3,544,399, using polycrystalline silicon as the masking material that remains in the gate region for the final formation of the gate electrode. Since such structures are insulating layer field effect transistors, a layer of an insulating material, e.g. of silicon dioxide, under the silicon-containing masking layer.

On the other hand, the high temperature resistant material itself may already be an insulating material, e.g. Silicon nitride, which remains as a gate dielectric in the gate area. Associated methods of this type are discussed in U.S. Patent No. 3,444,858. The high-temperature resistant material, e.g. Silicon nitride or a double layer of silicon nitride over silicon dioxide, for edge definition of the source and drain regions adjoining the gate region; it remains as a thin gate dielectric in the final field effect transistor structure. For this purpose, a thick oxide layer is thermally grown over the source and drain, the silicon nitride layer present in the gate region serving as an oxidation-inhibiting mask to prevent the thin gate insulating layer from increasing in thickness. Finally, a conductive gate electrode is formed in the gate area, the thin silicon nitride layer or, after its removal, another thin insulating layer also serving to delimit the area provided as the gate area.

The main advance in such a self-aligned gate structure has been that it has improved the positioning of the gate electrode and gate insulating layer relative to the source and drain regions. Before using the self-aligned gate structures, the gate electrode had to be made larger relative to the channel length effective between the source and drain, i.e. there was a significant overlap between the gate electrode and the source and drain regions. This resulted in undesired stray capacitances in the form of gate overlap capacitances, which led to a deterioration in the frequency properties or the switching speed of such field-effect transistor components in integrated circuits.

Although the self-aligned gate structures described above and the associated methods have already led to a considerable reduction in the gate overlap and thus to faster switching times, the problem of gate overlap of the source and drain regions has still not been completely eliminated. This was primarily due to the procedural design according to which the source and drain regions were formed by means of a diffusion step despite the provision of a self-aligned gate. Conventionally, this diffusion step can be carried out directly by introducing dopants for the source and drain into the semiconductor body in the presence of the self-adjusting gate masking. Alternatively, the dopants can first be introduced by diffusion or ion implantation in such a way that very flat surface areas of the appropriate conductivity type form, which is followed by a so-called driving-in step to be carried out at high temperatures, through which the source and drain are driven deeper into the semiconductor body. In the course of these diffusion or drive-in steps, of course, the doping atoms migrate to a certain extent below the gate masking layer. As a result, there was nevertheless an overlap of the gate with the source and drain and the resulting disadvantageous consequences.

It has also already been stated in the prior art, for example in US Pat. No. 3,472,712, to manufacture such self-aligned insulating layer field-effect transistors by avoiding any diffusion step simply by using an ion implantation. Such structures certainly have no gate overlap problems. However, the structures produced by such methods are subject to a restriction in that their source and drain regions only extend into the semiconductor body or the substrate with a depth of 200 to 300 nm or less. As a result, there are high resistance values for the source and drain regions, ie sheet resistances in the order of 50 n / D. Although such high layer resistance values can be quite acceptable for some discrete field effect transistor functions as well as for simpler integrated circuits, in the case of more complex integrated circuits built with field effect transistors, in which the source and drain regions or their extensions are used as part of the connection network, the layer wi is considerably lower resistances in the order of 8 to 10 Ω / □ are required. According to the prior art, source and drain regions with such a low sheet resistance were produced by one of the diffusion methods described above for forming the source and drain regions with a depth extension in the substrate in the order of magnitude of 1000 nm. The formation of, for example, 1000 nm deep source and drain areas only by ion implantation without subsequent diffusion treatment would, as far as possible, require a considerably more complicated process design, which is more complex in terms of the number of individual ion implantation steps and the associated choice of energy and dosage values.

The invention, as characterized in the claims, achieves the object of specifying a method for producing a semiconductor arrangement, in particular an insulating layer field-effect transistor structure, which is improved with respect to the overlap-free self-adjustment of doping regions relative to a surface layer, in which the overlap-free self-adjustment also occurs at a relatively deep in doping regions reaching the semiconductor body can be achieved. In summary, buried areas completely enclosed by the material of the semiconductor body are first formed in the mutual arrangement defined by the masking layer on the semiconductor surface by means of ion implantation, whereupon a subsequent heat treatment brings about a targeted expansion of the dopants present in the buried areas until the semiconductor surface is reached. In the case of an insulating layer field-effect transistor structure, this means that the source and drain are first doped as buried regions by means of ion implantation within the semiconductor body and the subsequent heat treatment for diffusing out the dopants is carried out to such an extent that the upper edge zone of the initially buried region ultimately just the semiconductor surface reached. In this case, it is ensured on the one hand that the channel region is always exactly and completely covered by the gate electrode, but on the other hand that there is no gate overlap with the source and drain regions formed in this way.

The invention is explained in more detail below with the aid of drawings which illustrate only one embodiment.

• Fig. 1-7 schematische Querschnittsdarstellungen durch eine Feldeffekttransistorstruktur zur Erläuterung der Verfahrensabfolge im Rahmen vorliegender Erfindung, und
• Fig. 8A-8C verschiedene Dotierungsprofile über die Tiefe des Draingebietes, wie sie sich zu verschiedenen Verfahrenszeitpunkten ergeben.

Show it :

• 1-7 are schematic cross-sectional representations through a field effect transistor structure to explain the process sequence within the scope of the present invention, and
• 8A-8C show different doping profiles over the depth of the drain region, as result at different times of the method.

1 shows a semiconductor body or a substrate 10 of the P conductivity type, the specific resistance value of which is approximately 0.1 to 1 Ω cm and on which an approximately 900 nm thick silicon dioxide layer 11 is formed. This layer 11 can be formed in a conventional manner by thermal oxidation or otherwise deposited, e.g. by vapor deposition or sputtering. An opening 12 is produced in layer 11 using conventional photoiitography and etching methods, so that the structure shown in FIG. 1 results.

According to FIG. 2, a thin layer 13 of silicon dioxide with a thickness of approximately 50 nm is then allowed to grow in the area of the opening 12, preferably thermally. A silicon layer 14 is applied over this by means of conventional methods for depositing silicon, for example described in US Pat. No. 3,424,629. This process step is carried out at a temperature on the order of 500 to 900 ° C and usually at atmospheric pressure. The silicon layer 14 is a polycrystalline structure since it is formed on the silicon dioxide layers 11 and 13. The thickness of the layer 14 is approximately 900 nm. Finally, an approximately 80 nm thick silicon dioxide layer 15 is produced in a conventional manner per se, but preferably by thermal oxidation of a part of the surface of the silicon layer 14.

3, using conventional photolithography and etching techniques and using a silicon dioxide masking layer 15 'on the area of the silicon layer 14 intended for the later gate electrode of the field effect transistor, a selective etching process is then carried out in order to remove the areas beyond the area 14' Silicon chip areas performed. All conventional chemical etching methods are available for the removal of the silicon layer 14, by means of which silicon can be etched, as opposed to silicon dioxide. For example, a dilute nitric acid / hydrofluoric acid solution is suitable for this purpose. As a result, a pair of openings 16 and 17 in FIG. 3 are obtained which are located at the locations intended for the later source and drain regions.

The regions 18 and 19 buried in the semiconductor body 10 are then formed by means of ion implantation in accordance with FIG. 4. For this purpose, N-type dopants, for example phosphorus, are implanted in the substrate. The implantation step can be carried out either directly through the unmasked, relatively thin silicon dioxide layer 13 or, as shown in FIG. 4, after the silicon dioxide layer 13 not covered by the silicon layer 14 'has been removed beforehand. 4, the silicon dioxide layer arranged below the mask in the form of the silicon layer 14 'is designated by 13'. To remove the silicon dioxide layer, a conventional etching process, for example under Buffered hydrofluoric acid can be used. In this case, the silicon dioxide layer 15 'will also be removed, while the layer 11, which is considerably thicker in comparison, remains essentially unchanged. The ion implantation must be carried out with sufficient radiation dosage and energy that the buried regions 18 and 19 have a concentration distribution which takes account of the following aspects. In the subsequent high-temperature step at about 1000 ° C. or higher for the outward diffusion of regions 18 and 19 down to the transitions 20 and 21 shown in FIG. 5, the same heat treatment is intended to ensure that regions 18 and 19 also move upwards expand in the direction of the surface of the semiconductor body 10 so that they just adjoin the silicon gate electrode laterally on the semiconductor surface. In order to obtain source and drain regions with relatively low sheet resistance values in the order of 8 to 10 Ω / □, penetration depths of the lower semiconductor junctions 20 and 21 in the order of 1 μm are desirable. In order to arrive at such resulting penetration depths, the initially implanted areas 18 and 19 in FIG. 4 should be generated with such beam energy and dosage that a concentration profile corresponding to FIG. 8A results. FIG. 8A shows the concentration distribution of the N-doping impurities for the regions 18 and 19 along the section line 8A-8A indicated in FIG. 4. As can be seen from FIG. 8A, regions 18 and 19 were originally created as regions completely enclosed in P-type semiconductor body 10, with a peak concentration being approximately at a distance of 0.5 μm from the semiconductor surface. The implantation step that can be used to form these areas 18 and 19 with the concentration profile shown can be carried out using conventional devices and methods, such as are described, for example, in US Pat. No. 3,756,862. For example, taking type ³ 'P ⁺ ions, an energy value of 400 keV and a dosage of approximately 10 ¹⁶ ions / cm ^{2 is} appropriate. The relatively thick layers 11 and 14 'prevent the implanted ions from being built into the semiconductor body 10 below these layers. The implantation also forms a dopant distribution similar to the shape shown in FIG. 8A in the silicon layer region 14 ′. As a result, the layer 14 'is desirably provided with a low sheet resistance.

Following the implantation step, a so-called diffusion or driving-in step is carried out at a temperature of about 950 ° C in a conventional oxidizing atmosphere, such as e.g. Steam is performed to bring the source and drain regions 18 and 19 into the form shown in FIG. 5. In particular, the area boundaries should thereby expand towards the semiconductor surface. The final dopant distribution for the source and drain regions 18 and 19 along the section line 8B-8B shown in FIG. 5 is shown in FIG. 8B. As a result of the oxidation process, a silicon dioxide layer 40 is formed over the semiconductor body 10 as well as over the polycrystalline silicon gate electrode 14 '.

In this context, it should be noted that if the peak concentration of the ion treatment is provided at a depth of penetration which is approximately half the depth of penetration which is ultimately desired for the lower region limits of source and drain, the source and drain region edges next to it due to the subsequent diffusion or heat treatment step their downward expansion to the same extent can also be extended upwards so that their intersections 22 and 23 (in FIG. 5) are practically exactly aligned with the corresponding edges 24 and 25 of the silicon gate electrode 14 'with regard to their lateral adjustment. To ensure that the intersections 22 and 23 coincide at least with the corners 24 and 25, or in other words that the silicon electrode 14 'and the underlying thin layer 13' of silicon dioxide extend to the intersections 22 and 23 the preliminary ion implantation step according to FIG. 8A has such a distribution that, following the diffusion or heat treatment, the final impurity concentration on the surface of regions 18 and 19 (point 26 in FIG. 8B) is up to a factor of 3 greater than that Basic doping (point 27 in FIG. 8B) of the silicon semiconductor body 10.

In the further course of the process, openings 31, 32 and 28 are then produced in the silicon dioxide layer 40 as contact openings for source, drain and the gate electrode. As can be seen from Figure 8B, the source and drain regions have a relatively low surface concentration of phosphorus. It is therefore advantageous to carry out a flat implantation of the dopants which cause the N-conduction type, for example phosphorus, in each of these contact openings, the regions designated 29, 30 and 34 being formed in FIG. 6. These areas have a high surface concentration of the N conductivity type in the order of 10 ²¹ atoms / cm ³ , cf. in addition the concentration profile shown in FIG. 8C for the relationships shown in FIG. 6, and in particular the point 33 in FIG. 8C. These N + conductive connection regions 29, 30 and 34 can be produced in a conventional manner by introducing dopants. However, it is preferable to fabricate these areas by implanting N-type ions, eg phosphorus, using the method described above with an energy of approximately 40 keV and a dosage of approximately 10 ¹¹ ions / cm ² . In the last method step, as shown in FIG. 7, is carried out in a conventional manner the contact and connection metallization in the form of the connections 35, 36 and 37 for source, drain and the silicon gate. This metallization can be completely conventional in the manner customary in such integrated FET circuits, for example made of aluminum. To the extent that a structure with a self-aligned silicon gate was used in the exemplary embodiment described, it should be noted that the invention is not restricted to this but can also be applied to other self-aligned gate designs. It should only be noted that the masking layer required to ensure the self-alignment of the thin gate insulating layer consists of a material that does not melt or decompose in any other way at the diffusion temperatures of the order of 1000 ° C. or greater that are used. Such other possibilities include, for example, self-aligned field effect transistors with silicon nitride gate technology, in which a thin layer of silicon nitride is used for the self-aligned formation of the source and drain regions relative to the thin gate insulating layer. Furthermore, metals such as molybdenum, tungsten or tantalum which are resistant to high temperatures can be used instead of the silicon described in the present exemplary embodiment in the context of such a method.

Claims (8)

1. Method for making a semiconductor device with selfalignment of doping regions relative to gate surface layers, in particular of an isolation layer field effect transistor structure, wherein, utilizing an ion implantation step, at least two doping regions of a second conductivity type, in particular source and drain regions, are formed with spacing between each other in a semiconductor body of a first conductivity type, and wherein on the semiconductor body at least in the area of said spacing, an ion beam masking layer is applied, characterized in that an ion beam generating the second conductivity type is permitted to act on the semiconductor body at energy and dosage levels sufficient to form buried regions (18, 19), which are initially fully enclosed within and oppositely doped to said semiconductor body (10), in the mutual structure (Fig. 4) defined by the masking layer (14'), and that by a subsequent heat treatment in the presence of masking layer (14') existing at least in the area of the spacing, the buried regions (18, 19) thus formed are caused to extend until they reach the semiconductor surface (Fig. 5).

2. Method in accordance with claim 1, characterized by a semiconductor body of silicon as well as by a masking layer defining the spacing between the doping regions, which comprises an electrically insulative layer on the semiconductor body and a layer of silicon formed thereon.

3. Method in accordance with claim 2, characterized in that the electrically insulative layer comprises silicon dioxide.

4. Method in accordance with any one of the preceding claims, characterized in that the masking layer comprises a layer of silicon nitride at least in the area of the spacing between the doping regions to be formed.

5. Method in accordance with any one of the preceding claims,. characterized in that the heat treatment is effected in such a manner that the semiconductor junctions (20, 21 in Fig. 5), belonging to the doping regions, in the course of their extension caused by the heat treatment intersect the semiconductor surface at the edge points (22, 23) of the masking layer (14') defining the spacing.

6. Method in accordance with any one of the preceding claims, characterized in that the surface concentration of the dopants determining the doping regions of the second conductivity type exceed by a factor of up to about 3 the background doping of the semiconductor body of the first conductivity type.

7. Method in accordance with any one of the preceding claims, characterized in that the ion implantation step is effected through a layer, preferably of silicon dioxide, covering the semiconductor surface in the area of the openings in the masking layer.

8. Method in accordance with any one of the preceding claims, characterized in that after formation of the contact openings to the doping regions and prior to the formation of the accompanying metalization, additional dopants of the second conductivity type for increasing the surface concentration, preferably also using an ion implantation step, are introduced into the exposed regions in the area of the contact openings (28, 31, 32 in Fig. 6).

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