DE69939794D1 - Anschlussfläche für Flipchip-Bonding - Google Patents
Anschlussfläche für Flipchip-BondingInfo
- Publication number
- DE69939794D1 DE69939794D1 DE69939794T DE69939794T DE69939794D1 DE 69939794 D1 DE69939794 D1 DE 69939794D1 DE 69939794 T DE69939794 T DE 69939794T DE 69939794 T DE69939794 T DE 69939794T DE 69939794 D1 DE69939794 D1 DE 69939794D1
- Authority
- DE
- Germany
- Prior art keywords
- flip
- pad
- chip bonding
- bonding
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/0929—Conductive planes
- H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10125390A JPH11307886A (ja) | 1998-04-21 | 1998-04-21 | フリップチップ接合ランドうねり防止パターン |
Publications (1)
Publication Number | Publication Date |
---|---|
DE69939794D1 true DE69939794D1 (de) | 2008-12-11 |
Family
ID=14908963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69939794T Expired - Lifetime DE69939794D1 (de) | 1998-04-21 | 1999-04-13 | Anschlussfläche für Flipchip-Bonding |
Country Status (5)
Country | Link |
---|---|
US (1) | US6291775B1 (de) |
EP (1) | EP0954020B1 (de) |
JP (1) | JPH11307886A (de) |
CN (1) | CN1146977C (de) |
DE (1) | DE69939794D1 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1895587A3 (de) * | 1997-10-17 | 2013-04-03 | Ibiden Co., Ltd. | Substrat für eine Halbleiterpackung |
US6759596B1 (en) * | 2000-05-12 | 2004-07-06 | Shipley Company | Sequential build circuit board |
US6683387B1 (en) * | 2000-06-15 | 2004-01-27 | Advanced Micro Devices, Inc. | Flip chip carrier package with adapted landing pads |
US6894399B2 (en) * | 2001-04-30 | 2005-05-17 | Intel Corporation | Microelectronic device having signal distribution functionality on an interfacial layer thereof |
US6888240B2 (en) * | 2001-04-30 | 2005-05-03 | Intel Corporation | High performance, low cost microelectronic circuit package with interposer |
SG122743A1 (en) * | 2001-08-21 | 2006-06-29 | Micron Technology Inc | Microelectronic devices and methods of manufacture |
SG104293A1 (en) | 2002-01-09 | 2004-06-21 | Micron Technology Inc | Elimination of rdl using tape base flip chip on flex for die stacking |
SG111935A1 (en) | 2002-03-04 | 2005-06-29 | Micron Technology Inc | Interposer configured to reduce the profiles of semiconductor device assemblies and packages including the same and methods |
SG115459A1 (en) * | 2002-03-04 | 2005-10-28 | Micron Technology Inc | Flip chip packaging using recessed interposer terminals |
US6975035B2 (en) * | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
JP4222882B2 (ja) * | 2003-06-03 | 2009-02-12 | 日東電工株式会社 | 配線回路基板 |
TWM243783U (en) * | 2003-06-30 | 2004-09-11 | Innolux Display Corp | Structure of chip on glass |
DE10339609A1 (de) * | 2003-08-28 | 2005-03-24 | Forschungszentrum Karlsruhe Gmbh | Oligonukleotid, Verfahren und System zur Detektion von Antibiotikaresistenz-vermittelnden Genen in Mikroorganismen mittels der Echtzeit-PCR |
KR100975521B1 (ko) * | 2003-10-04 | 2010-08-12 | 삼성전자주식회사 | 발광 소자 조립체 |
KR100730077B1 (ko) * | 2005-11-25 | 2007-06-19 | 삼성전기주식회사 | 이미지센서 모듈과 카메라모듈 패키지 |
JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
US7679002B2 (en) * | 2006-08-22 | 2010-03-16 | Texas Instruments Incorporated | Semiconductive device having improved copper density for package-on-package applications |
JP4996193B2 (ja) * | 2006-10-06 | 2012-08-08 | ルネサスエレクトロニクス株式会社 | 配線基板、半導体パッケージ |
US8963016B2 (en) * | 2008-10-31 | 2015-02-24 | Taiyo Yuden Co., Ltd. | Printed wiring board and method for manufacturing same |
TWI389604B (zh) * | 2008-12-29 | 2013-03-11 | Au Optronics Corp | 電路板結構與其製造方法及液晶顯示器 |
TWI455263B (zh) * | 2009-02-16 | 2014-10-01 | Ind Tech Res Inst | 晶片封裝結構及晶片封裝方法 |
KR101007328B1 (ko) | 2009-05-12 | 2011-01-13 | 삼성전기주식회사 | 카메라 모듈용 인쇄회로기판 및 카메라 모듈 |
US20160154234A1 (en) * | 2014-03-24 | 2016-06-02 | Gerald McMorrow | Enhanced closed loop, optical feedback synchronization system for imaging applications |
EP3277065B1 (de) * | 2015-03-27 | 2021-08-11 | Kyocera Corporation | Bildgebungskomponente und bildgebungsmodul damit |
US9972590B2 (en) * | 2016-07-05 | 2018-05-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Semiconductor package having a solder-on-pad structure |
JP7260220B2 (ja) * | 2019-02-26 | 2023-04-18 | 日清紡マイクロデバイス株式会社 | 半導体装置 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052084A (ja) * | 1983-08-31 | 1985-03-23 | 株式会社東芝 | 印刷配線基板 |
JPH02143583A (ja) * | 1988-11-25 | 1990-06-01 | Mitsubishi Electric Corp | メモリモジュール |
JPH0690068A (ja) * | 1992-09-08 | 1994-03-29 | Ibiden Co Ltd | プリント配線板 |
US5510758A (en) * | 1993-04-07 | 1996-04-23 | Matsushita Electric Industrial Co., Ltd. | Multilayer microstrip wiring board with a semiconductor device mounted thereon via bumps |
JP3383398B2 (ja) * | 1994-03-22 | 2003-03-04 | 株式会社東芝 | 半導体パッケージ |
KR100194130B1 (ko) * | 1994-03-30 | 1999-06-15 | 니시무로 타이죠 | 반도체 패키지 |
JPH07302858A (ja) * | 1994-04-28 | 1995-11-14 | Toshiba Corp | 半導体パッケージ |
JP3608226B2 (ja) * | 1994-08-26 | 2005-01-05 | 富士通株式会社 | 半導体チップの実装方法及び半導体装置 |
JP3202525B2 (ja) * | 1995-03-27 | 2001-08-27 | キヤノン株式会社 | 電気回路基板及びそれを備えた表示装置 |
JPH09223715A (ja) * | 1996-02-15 | 1997-08-26 | Pfu Ltd | フリップチップまたはフリップチップキャリアの接続構造 |
JPH09321390A (ja) * | 1996-05-31 | 1997-12-12 | Olympus Optical Co Ltd | 両面フレキシブル配線板 |
JPH1013003A (ja) * | 1996-06-26 | 1998-01-16 | Casio Comput Co Ltd | 半導体装置 |
JP2845219B2 (ja) * | 1996-10-07 | 1999-01-13 | セイコーエプソン株式会社 | 電気的接続構造及び液晶装置 |
US5900312A (en) * | 1996-11-08 | 1999-05-04 | W. L. Gore & Associates, Inc. | Integrated circuit chip package assembly |
JPH10163386A (ja) * | 1996-12-03 | 1998-06-19 | Toshiba Corp | 半導体装置、半導体パッケージおよび実装回路装置 |
-
1998
- 1998-04-21 JP JP10125390A patent/JPH11307886A/ja active Pending
-
1999
- 1999-04-13 EP EP99107191A patent/EP0954020B1/de not_active Expired - Lifetime
- 1999-04-13 DE DE69939794T patent/DE69939794D1/de not_active Expired - Lifetime
- 1999-04-14 US US09/291,314 patent/US6291775B1/en not_active Expired - Fee Related
- 1999-04-21 CN CNB991051572A patent/CN1146977C/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1233849A (zh) | 1999-11-03 |
EP0954020A2 (de) | 1999-11-03 |
US6291775B1 (en) | 2001-09-18 |
EP0954020B1 (de) | 2008-10-29 |
EP0954020A3 (de) | 2000-12-27 |
CN1146977C (zh) | 2004-04-21 |
JPH11307886A (ja) | 1999-11-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8327 | Change in the person/name/address of the patent owner |
Owner name: PANASONIC CORPORATION, KADOMA-SHI, OSAKA, JP |
|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: PANASONIC CORP., KADOMA, OSAKA, JP |