DE69918338D1 - Mikroelektronischer chip - Google Patents

Mikroelektronischer chip

Info

Publication number
DE69918338D1
DE69918338D1 DE69918338T DE69918338T DE69918338D1 DE 69918338 D1 DE69918338 D1 DE 69918338D1 DE 69918338 T DE69918338 T DE 69918338T DE 69918338 T DE69918338 T DE 69918338T DE 69918338 D1 DE69918338 D1 DE 69918338D1
Authority
DE
Germany
Prior art keywords
microelectronic chip
microelectronic
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69918338T
Other languages
English (en)
Other versions
DE69918338T2 (de
Inventor
Satish Soman
Zbigniew Opalka
Mukesh Chatter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nexabit Networks Inc
Original Assignee
Nexabit Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nexabit Networks Inc filed Critical Nexabit Networks Inc
Publication of DE69918338D1 publication Critical patent/DE69918338D1/de
Application granted granted Critical
Publication of DE69918338T2 publication Critical patent/DE69918338T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
DE69918338T 1998-10-29 1999-10-26 Mikroelektronischer chip Expired - Fee Related DE69918338T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/182,268 US6237130B1 (en) 1998-10-29 1998-10-29 Chip layout for implementing arbitrated high speed switching access of pluralities of I/O data ports to internally cached DRAM banks and the like
US182268 1998-10-29
PCT/IB1999/001732 WO2000026917A1 (en) 1998-10-29 1999-10-26 Microelectronic chips

Publications (2)

Publication Number Publication Date
DE69918338D1 true DE69918338D1 (de) 2004-07-29
DE69918338T2 DE69918338T2 (de) 2005-08-18

Family

ID=22667740

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69918338T Expired - Fee Related DE69918338T2 (de) 1998-10-29 1999-10-26 Mikroelektronischer chip

Country Status (6)

Country Link
US (1) US6237130B1 (de)
EP (1) EP1166272B1 (de)
AU (1) AU6224499A (de)
CA (1) CA2348983A1 (de)
DE (1) DE69918338T2 (de)
WO (1) WO2000026917A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4363716B2 (ja) * 1999-06-25 2009-11-11 株式会社東芝 Ｌｓｉの配線構造の設計方法
US6493855B1 (en) * 2000-02-18 2002-12-10 Hewlett-Packard Company Flexible cache architecture using modular arrays
US6643165B2 (en) * 2001-07-25 2003-11-04 Nantero, Inc. Electromechanical memory having cell selection circuitry constructed with nanotube technology
US6706402B2 (en) 2001-07-25 2004-03-16 Nantero, Inc. Nanotube films and articles
US6835591B2 (en) * 2001-07-25 2004-12-28 Nantero, Inc. Methods of nanotube films and articles
US6574130B2 (en) * 2001-07-25 2003-06-03 Nantero, Inc. Hybrid circuit having nanotube electromechanical memory
US6919592B2 (en) * 2001-07-25 2005-07-19 Nantero, Inc. Electromechanical memory array using nanotube ribbons and method for making same
US7176505B2 (en) * 2001-12-28 2007-02-13 Nantero, Inc. Electromechanical three-trace junction devices
US6784028B2 (en) 2001-12-28 2004-08-31 Nantero, Inc. Methods of making electromechanical three-trace junction devices
US6799304B2 (en) * 2002-10-01 2004-09-28 Lsi Logic Corporation Arbitration within a multiport AMBA slave
US6996785B1 (en) 2003-04-25 2006-02-07 Universal Network Machines, Inc . On-chip packet-based interconnections using repeaters/routers
US6977656B1 (en) 2003-07-28 2005-12-20 Neomagic Corp. Two-layer display-refresh and video-overlay arbitration of both DRAM and SRAM memories
US7848153B2 (en) * 2008-08-19 2010-12-07 Qimonda Ag High speed memory architecture
US8901747B2 (en) 2010-07-29 2014-12-02 Mosys, Inc. Semiconductor chip layout
TWI493568B (zh) 2013-08-19 2015-07-21 Ind Tech Res Inst 記憶體裝置
US11600307B2 (en) * 2020-12-29 2023-03-07 Qualcomm Incorporated Memory circuit architecture

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438681A (en) * 1993-08-24 1995-08-01 Mensch, Jr.; William D. Topography for CMOS microcomputer
US5799209A (en) * 1995-12-29 1998-08-25 Chatter; Mukesh Multi-port internally cached DRAM system utilizing independent serial interfaces and buffers arbitratively connected under a dynamic configuration
US5790839A (en) * 1996-12-20 1998-08-04 International Business Machines Corporation System integration of DRAM macros and logic cores in a single chip architecture
US6088760A (en) * 1997-03-07 2000-07-11 Mitsubishi Semiconductor America, Inc. Addressing system in a multi-port RAM having main and cache memories
US5835932A (en) * 1997-03-13 1998-11-10 Silicon Aquarius, Inc. Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM
US5953738A (en) * 1997-07-02 1999-09-14 Silicon Aquarius, Inc DRAM with integral SRAM and arithmetic-logic units
US6088785A (en) * 1998-04-15 2000-07-11 Diamond Multimedia Systems, Inc. Method of configuring a functionally redefinable signal processing system

Also Published As

Publication number Publication date
EP1166272B1 (de) 2004-06-23
EP1166272A1 (de) 2002-01-02
CA2348983A1 (en) 2000-05-11
AU6224499A (en) 2000-05-22
WO2000026917A1 (en) 2000-05-11
US6237130B1 (en) 2001-05-22
DE69918338T2 (de) 2005-08-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee