DE69930027T2 - Metallisierungsverfahren für Halbleiter - Google Patents

Metallisierungsverfahren für Halbleiter Download PDF

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Publication number
DE69930027T2
DE69930027T2 DE69930027T DE69930027T DE69930027T2 DE 69930027 T2 DE69930027 T2 DE 69930027T2 DE 69930027 T DE69930027 T DE 69930027T DE 69930027 T DE69930027 T DE 69930027T DE 69930027 T2 DE69930027 T2 DE 69930027T2
Authority
DE
Germany
Prior art keywords
dielectric layer
metallization
layer
portions
incisions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69930027T
Other languages
German (de)
English (en)
Other versions
DE69930027D1 (de
Inventor
Young-Jin Poughkeepsie Park
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE69930027D1 publication Critical patent/DE69930027D1/de
Application granted granted Critical
Publication of DE69930027T2 publication Critical patent/DE69930027T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69930027T 1998-06-17 1999-05-31 Metallisierungsverfahren für Halbleiter Expired - Lifetime DE69930027T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99093 1998-06-17
US09/099,093 US6137178A (en) 1998-06-17 1998-06-17 Semiconductor metalization system and method

Publications (2)

Publication Number Publication Date
DE69930027D1 DE69930027D1 (de) 2006-04-27
DE69930027T2 true DE69930027T2 (de) 2006-09-14

Family

ID=22272661

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69930027T Expired - Lifetime DE69930027T2 (de) 1998-06-17 1999-05-31 Metallisierungsverfahren für Halbleiter

Country Status (7)

Country Link
US (1) US6137178A (https=)
EP (1) EP0966035B1 (https=)
JP (1) JP2000031280A (https=)
KR (1) KR100598256B1 (https=)
CN (1) CN1139112C (https=)
DE (1) DE69930027T2 (https=)
TW (1) TW417204B (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2786609B1 (fr) * 1998-11-26 2003-10-17 St Microelectronics Sa Circuit integre a capacite interlignes reduite et procede de fabrication associe
US20060017162A1 (en) * 1999-03-12 2006-01-26 Shoji Seta Semiconductor device and manufacturing method of the same
US6849923B2 (en) 1999-03-12 2005-02-01 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method of the same
US6420252B1 (en) * 2000-05-10 2002-07-16 Emcore Corporation Methods of forming robust metal contacts on compound semiconductors
US7892962B2 (en) * 2007-09-05 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Nail-shaped pillar for wafer-level chip-scale packaging
JP2011527830A (ja) * 2008-07-09 2011-11-04 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 導体間隙が縮小された超小型電子相互接続素子
US8309446B2 (en) 2008-07-16 2012-11-13 Applied Materials, Inc. Hybrid heterojunction solar cell fabrication using a doping layer mask
WO2010068331A1 (en) 2008-12-10 2010-06-17 Applied Materials, Inc. Enhanced vision system for screen printing pattern alignment
US9064968B2 (en) * 2013-08-19 2015-06-23 Phison Electronics Corp. Non-volatile memory device and operation and fabricating methods thereof
US8772951B1 (en) 2013-08-29 2014-07-08 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
US9159670B2 (en) 2013-08-29 2015-10-13 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
KR102377372B1 (ko) * 2014-04-02 2022-03-21 어플라이드 머티어리얼스, 인코포레이티드 인터커넥트들을 형성하기 위한 방법
US20190067178A1 (en) * 2017-08-30 2019-02-28 Qualcomm Incorporated Fine pitch and spacing interconnects with reserve interconnect portion

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057975B2 (ja) * 1993-09-27 2000-07-04 日本電気株式会社 集積回路の配線
US5471093A (en) * 1994-10-28 1995-11-28 Advanced Micro Devices, Inc. Pseudo-low dielectric constant technology
JPH08293523A (ja) * 1995-02-21 1996-11-05 Seiko Epson Corp 半導体装置およびその製造方法
US5702982A (en) * 1996-03-28 1997-12-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making metal contacts and interconnections concurrently on semiconductor integrated circuits
US5846876A (en) * 1996-06-05 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit which uses a damascene process for producing staggered interconnect lines
US5753976A (en) * 1996-06-14 1998-05-19 Minnesota Mining And Manufacturing Company Multi-layer circuit having a via matrix interlayer connection
KR100219508B1 (ko) * 1996-12-30 1999-09-01 윤종용 반도체장치의 금속배선층 형성방법

Also Published As

Publication number Publication date
CN1139112C (zh) 2004-02-18
KR100598256B1 (ko) 2006-07-07
DE69930027D1 (de) 2006-04-27
TW417204B (en) 2001-01-01
JP2000031280A (ja) 2000-01-28
EP0966035B1 (en) 2006-03-01
KR20000006238A (ko) 2000-01-25
CN1254949A (zh) 2000-05-31
US6137178A (en) 2000-10-24
EP0966035A1 (en) 1999-12-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE