DE69906406D1 - Reparierbare integrierte Halbleiterspeicherschaltung mit selektiver Zuweisung von Redundanzgruppen zu Domänen - Google Patents

Reparierbare integrierte Halbleiterspeicherschaltung mit selektiver Zuweisung von Redundanzgruppen zu Domänen

Info

Publication number
DE69906406D1
DE69906406D1 DE69906406T DE69906406T DE69906406D1 DE 69906406 D1 DE69906406 D1 DE 69906406D1 DE 69906406 T DE69906406 T DE 69906406T DE 69906406 T DE69906406 T DE 69906406T DE 69906406 D1 DE69906406 D1 DE 69906406D1
Authority
DE
Germany
Prior art keywords
domains
semiconductor memory
memory circuit
integrated semiconductor
redundancy groups
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69906406T
Other languages
English (en)
Other versions
DE69906406T2 (de
Inventor
Toshiaki Kirihata
Karl-Peter Pfefferl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Siemens AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, International Business Machines Corp filed Critical Siemens AG
Application granted granted Critical
Publication of DE69906406D1 publication Critical patent/DE69906406D1/de
Publication of DE69906406T2 publication Critical patent/DE69906406T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/812—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a reduced amount of fuses
DE69906406T 1998-02-02 1999-01-29 Reparierbare integrierte Halbleiterspeicherschaltung mit selektiver Zuweisung von Redundanzgruppen zu Domänen Expired - Fee Related DE69906406T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17019 1998-02-02
US09/017,019 US5970000A (en) 1998-02-02 1998-02-02 Repairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domains

Publications (2)

Publication Number Publication Date
DE69906406D1 true DE69906406D1 (de) 2003-05-08
DE69906406T2 DE69906406T2 (de) 2004-01-08

Family

ID=21780275

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69906406T Expired - Fee Related DE69906406T2 (de) 1998-02-02 1999-01-29 Reparierbare integrierte Halbleiterspeicherschaltung mit selektiver Zuweisung von Redundanzgruppen zu Domänen

Country Status (4)

Country Link
US (1) US5970000A (de)
EP (1) EP0933709B1 (de)
JP (1) JP3254432B2 (de)
DE (1) DE69906406T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100621265B1 (ko) * 1998-04-17 2006-09-13 인피니언 테크놀로지스 아게 리던던트 기억 셀을 갖는 메모리 장치 및 리던던트 기억 셀에 액세스하기 위한 방법
US6052318A (en) * 1998-12-22 2000-04-18 Siemens Aktiengesellschaft Repairable semiconductor memory circuit having parrel redundancy replacement wherein redundancy elements replace failed elements
US7062425B1 (en) * 1999-09-30 2006-06-13 Cypress Semiconductor Corp. Method and apparatus for automated enumeration, simulation, identification and/or irradiation of device attributes
US6181614B1 (en) * 1999-11-12 2001-01-30 International Business Machines Corporation Dynamic repair of redundant memory array
DE10051167B4 (de) 2000-10-16 2007-10-25 Infineon Technologies Ag Anordnung zur Fuseinitialisierung
KR100375998B1 (ko) * 2000-11-17 2003-03-15 (주)실리콘세븐 자동 테스트 및 리페어 기능을 내장하는 반도체 메모리장치 및 그 방법
JP2003077282A (ja) * 2001-08-31 2003-03-14 Fujitsu Ltd 不揮発性半導体記憶装置
US7925938B2 (en) * 2001-10-12 2011-04-12 Geneticware Co. Ltd. Structure and method of repairing SDRAM by generating slicing table of fault distribution
JP2004127475A (ja) * 2002-07-29 2004-04-22 Renesas Technology Corp 半導体記憶装置
US7076703B1 (en) * 2002-11-26 2006-07-11 Advanced Micro Devices, Inc. Method and system for defining a redundancy window around a particular column in a memory array
US6809972B2 (en) * 2003-03-13 2004-10-26 Infineon Technologies Ag Circuit technique for column redundancy fuse latches
US6882583B2 (en) * 2003-04-30 2005-04-19 International Business Machines Corporation Method and apparatus for implementing DRAM redundancy fuse latches using SRAM
US7523257B2 (en) * 2003-08-27 2009-04-21 Adaptec, Inc. Method of managing raid level bad blocks in a networked storage system
KR100554986B1 (ko) * 2003-12-30 2006-03-03 주식회사 하이닉스반도체 효율적으로 에러셀을 리페어 할 수 있는 반도체 메모리 장치
US7458616B2 (en) * 2004-12-30 2008-12-02 Hydril Company Threads with perturbations
DE102006019075B4 (de) * 2006-04-25 2008-01-31 Infineon Technologies Ag Integrierte Schaltung zur Speicherung eines Datums
JP2013131273A (ja) * 2011-12-21 2013-07-04 Fujitsu Ltd 半導体集積回路及び半導体集積回路の試験方法
KR20170055222A (ko) 2015-11-11 2017-05-19 삼성전자주식회사 리페어 단위 변경 기능을 가지는 메모리 장치 및 메모리 시스템

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0465808B1 (de) * 1990-06-19 1998-07-29 Texas Instruments Incorporated Assoziatives DRAM-Redundanzschema mit variabler Satzgrösse
JPH0831279B2 (ja) * 1990-12-20 1996-03-27 インターナショナル・ビジネス・マシーンズ・コーポレイション 冗長システム
US5295101A (en) * 1992-01-31 1994-03-15 Texas Instruments Incorporated Array block level redundancy with steering logic
JP3040625B2 (ja) * 1992-02-07 2000-05-15 松下電器産業株式会社 半導体記憶装置
EP0636258B1 (de) * 1992-04-16 1996-03-27 Siemens Aktiengesellschaft Integrierter halbleiterspeicher mit redundanzeinrichtung
JPH0696598A (ja) * 1992-07-10 1994-04-08 Texas Instr Japan Ltd 半導体メモリ装置及び欠陥メモリセル救済回路
ATE200939T1 (de) * 1993-02-19 2001-05-15 Infineon Technologies Ag Spalten-redundanz-schaltungsanordnung für einen speicher
US5422850A (en) * 1993-07-12 1995-06-06 Texas Instruments Incorporated Semiconductor memory device and defective memory cell repair circuit
US5491664A (en) * 1993-09-27 1996-02-13 Cypress Semiconductor Corporation Flexibilitiy for column redundancy in a divided array architecture
KR960008825B1 (en) * 1993-11-18 1996-07-05 Samsung Electronics Co Ltd Row redundancy circuit and method of semiconductor memory device with double row decoder
JP3351595B2 (ja) * 1993-12-22 2002-11-25 株式会社日立製作所 半導体メモリ装置
JPH08180698A (ja) * 1994-12-22 1996-07-12 Toshiba Corp 半導体記憶装置
US5881003A (en) * 1997-07-16 1999-03-09 International Business Machines Corporation Method of making a memory device fault tolerant using a variable domain redundancy replacement configuration

Also Published As

Publication number Publication date
US5970000A (en) 1999-10-19
JPH11273394A (ja) 1999-10-08
JP3254432B2 (ja) 2002-02-04
EP0933709A3 (de) 2000-02-02
EP0933709A2 (de) 1999-08-04
EP0933709B1 (de) 2003-04-02
DE69906406T2 (de) 2004-01-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US