DE69839721D1 - Veraschungsverfahren - Google Patents

Veraschungsverfahren

Info

Publication number
DE69839721D1
DE69839721D1 DE69839721T DE69839721T DE69839721D1 DE 69839721 D1 DE69839721 D1 DE 69839721D1 DE 69839721 T DE69839721 T DE 69839721T DE 69839721 T DE69839721 T DE 69839721T DE 69839721 D1 DE69839721 D1 DE 69839721D1
Authority
DE
Germany
Prior art keywords
ashing process
ashing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69839721T
Other languages
English (en)
Inventor
Takashi Kurimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69839721D1 publication Critical patent/DE69839721D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
DE69839721T 1997-09-19 1998-03-16 Veraschungsverfahren Expired - Fee Related DE69839721D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25556497A JP3318241B2 (ja) 1997-09-19 1997-09-19 アッシング方法

Publications (1)

Publication Number Publication Date
DE69839721D1 true DE69839721D1 (de) 2008-08-28

Family

ID=17280481

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69839721T Expired - Fee Related DE69839721D1 (de) 1997-09-19 1998-03-16 Veraschungsverfahren

Country Status (6)

Country Link
US (1) US6043004A (de)
EP (1) EP0910118B1 (de)
JP (1) JP3318241B2 (de)
KR (1) KR100298259B1 (de)
DE (1) DE69839721D1 (de)
TW (1) TW382745B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417080B1 (en) * 1999-01-28 2002-07-09 Canon Kabushiki Kaisha Method of processing residue of ion implanted photoresist, and method of producing semiconductor device
JP3449535B2 (ja) * 1999-04-22 2003-09-22 ソニー株式会社 半導体素子の製造方法
US6235453B1 (en) * 1999-07-07 2001-05-22 Advanced Micro Devices, Inc. Low-k photoresist removal process
US20050022839A1 (en) * 1999-10-20 2005-02-03 Savas Stephen E. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
US20010027023A1 (en) * 2000-02-15 2001-10-04 Shigenori Ishihara Organic substance removing methods, methods of producing semiconductor device, and organic substance removing apparatuses
US6543617B2 (en) 2001-03-09 2003-04-08 International Business Machines Corporation Packaged radiation sensitive coated workpiece process for making and method of storing same
US6831018B2 (en) 2001-08-21 2004-12-14 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device
JP4838464B2 (ja) 2001-09-26 2011-12-14 東京エレクトロン株式会社 処理方法
JP2003163212A (ja) * 2001-11-27 2003-06-06 Nec Electronics Corp 半導体装置の製造方法
US6680164B2 (en) 2001-11-30 2004-01-20 Applied Materials Inc. Solvent free photoresist strip and residue removal processing for post etching of low-k films
KR100570205B1 (ko) * 2001-12-18 2006-04-12 주식회사 하이닉스반도체 반도체 소자의 감광막 제거방법
US20030215962A1 (en) * 2002-05-14 2003-11-20 Applied Materials, Inc. Integration of multiple processes within a single chamber
US6924157B1 (en) * 2002-10-21 2005-08-02 Advanced Micro Devices, Inc. Real time particle monitor inside of plasma chamber during resist strip processing
US6897162B2 (en) * 2003-10-20 2005-05-24 Wafermasters, Inc. Integrated ashing and implant annealing method
US20050158667A1 (en) * 2004-01-20 2005-07-21 Applied Materials, Inc. Solvent free photoresist strip and residue removal processing for post etching of low-k films
US20070186953A1 (en) * 2004-07-12 2007-08-16 Savas Stephen E Systems and Methods for Photoresist Strip and Residue Treatment in Integrated Circuit Manufacturing
US20060042752A1 (en) * 2004-08-30 2006-03-02 Rueger Neal R Plasma processing apparatuses and methods
KR100661373B1 (ko) 2004-12-30 2006-12-27 매그나칩 반도체 유한회사 광촉매를 이용한 에싱 방법 및 에싱 장치
JP5011852B2 (ja) 2005-07-20 2012-08-29 富士通セミコンダクター株式会社 電子デバイスの製造方法
JP4739917B2 (ja) * 2005-11-07 2011-08-03 富士通セミコンダクター株式会社 レジストマスクの剥離方法
KR100736126B1 (ko) 2005-12-28 2007-07-06 동부일렉트로닉스 주식회사 반도체 소자 제조 방법
US20080261384A1 (en) * 2007-04-18 2008-10-23 United Microelectronics Corp. Method of removing photoresist layer and method of fabricating semiconductor device using the same
JP5457109B2 (ja) 2009-09-02 2014-04-02 東京エレクトロン株式会社 プラズマ処理装置
JP2013098054A (ja) * 2011-11-01 2013-05-20 Ulvac Japan Ltd マイクロ波導入装置
JP2015037166A (ja) * 2013-08-16 2015-02-23 株式会社アルバック レジスト剥離方法およびレジスト剥離装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
JPH0760820B2 (ja) * 1987-10-29 1995-06-28 日本電気株式会社 半導体製造装置
US5226056A (en) * 1989-01-10 1993-07-06 Nihon Shinku Gijutsu Kabushiki Kaisha Plasma ashing method and apparatus therefor
JP2785027B2 (ja) * 1989-01-10 1998-08-13 日本真空技術株式会社 プラズマアッシング方法
JPH04286317A (ja) * 1991-03-15 1992-10-12 Fujitsu Ltd 半導体装置のアッシング方法及びアッシング装置
JPH04352157A (ja) * 1991-05-30 1992-12-07 Toyota Autom Loom Works Ltd レジスト除去方法
JP3247722B2 (ja) * 1992-04-15 2002-01-21 東京応化工業株式会社 プラズマアッシング方法
JP3391410B2 (ja) * 1993-09-17 2003-03-31 富士通株式会社 レジストマスクの除去方法
JPH0869896A (ja) * 1994-08-30 1996-03-12 Sony Corp プラズマ処理装置およびプラズマ処理方法
JPH08288260A (ja) * 1995-04-18 1996-11-01 Sony Corp ヘリコン波プラズマ・アッシング方法
JPH0936103A (ja) * 1995-07-18 1997-02-07 Ulvac Japan Ltd 半導体ウェハのエッチング及びレジスト除去のための方法並びに装置
US5795831A (en) * 1996-10-16 1998-08-18 Ulvac Technologies, Inc. Cold processes for cleaning and stripping photoresist from surfaces of semiconductor wafers
US5811358A (en) * 1997-01-03 1998-09-22 Mosel Vitelic Inc. Low temperature dry process for stripping photoresist after high dose ion implantation

Also Published As

Publication number Publication date
JPH1197421A (ja) 1999-04-09
KR100298259B1 (ko) 2001-10-25
US6043004A (en) 2000-03-28
TW382745B (en) 2000-02-21
JP3318241B2 (ja) 2002-08-26
KR19990029149A (ko) 1999-04-26
EP0910118B1 (de) 2008-07-16
EP0910118A1 (de) 1999-04-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee