DE69827949D1 - Gerät und verfahren um speicherfehler zu erkennen und zu berichten - Google Patents

Gerät und verfahren um speicherfehler zu erkennen und zu berichten

Info

Publication number
DE69827949D1
DE69827949D1 DE69827949T DE69827949T DE69827949D1 DE 69827949 D1 DE69827949 D1 DE 69827949D1 DE 69827949 T DE69827949 T DE 69827949T DE 69827949 T DE69827949 T DE 69827949T DE 69827949 D1 DE69827949 D1 DE 69827949D1
Authority
DE
Germany
Prior art keywords
error
memory
register
detection signal
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69827949T
Other languages
English (en)
Other versions
DE69827949T2 (de
Inventor
Matthew Brisse
Richard Gerard Kress
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
OL Security LLC
Original Assignee
Intergraph Hardware Technologies Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intergraph Hardware Technologies Co filed Critical Intergraph Hardware Technologies Co
Publication of DE69827949D1 publication Critical patent/DE69827949D1/de
Application granted granted Critical
Publication of DE69827949T2 publication Critical patent/DE69827949T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1024—Identification of the type of error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
DE69827949T 1997-07-28 1998-07-28 Gerät und verfahren um speicherfehler zu erkennen und zu berichten Expired - Lifetime DE69827949T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US5389297P 1997-07-28 1997-07-28
US53892P 1997-07-28
PCT/US1998/015613 WO1999005599A1 (en) 1997-07-28 1998-07-28 Apparatus and method for memory error detection and error reporting

Publications (2)

Publication Number Publication Date
DE69827949D1 true DE69827949D1 (de) 2005-01-05
DE69827949T2 DE69827949T2 (de) 2005-10-27

Family

ID=21987259

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69827949T Expired - Lifetime DE69827949T2 (de) 1997-07-28 1998-07-28 Gerät und verfahren um speicherfehler zu erkennen und zu berichten

Country Status (4)

Country Link
US (1) US6158025A (de)
EP (1) EP1000395B1 (de)
DE (1) DE69827949T2 (de)
WO (1) WO1999005599A1 (de)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11242850A (ja) * 1998-02-25 1999-09-07 Hitachi Ltd リアルタイムデータ記録方式
US6356917B1 (en) * 1998-07-17 2002-03-12 Ncr Corporation Monitoring and raising alerts for database jobs
FR2784475B1 (fr) * 1998-10-12 2000-12-29 Centre Nat Etd Spatiales Procede de traitement d'un systeme electronique soumis a des contraintes d'erreurs transitoires
EP1153395A4 (de) * 1998-12-30 2002-04-17 Intel Corp Organisation eines speicherbausteins
US6543010B1 (en) * 1999-02-24 2003-04-01 Hewlett-Packard Development Company, L.P. Method and apparatus for accelerating a memory dump
US6701451B1 (en) * 2000-08-11 2004-03-02 Emc Corporation Selective correction of data errors
US20030051193A1 (en) * 2001-09-10 2003-03-13 Dell Products L.P. Computer system with improved error detection
JP3722057B2 (ja) * 2001-11-30 2005-11-30 ソニー株式会社 データ記録再生装置及びデータ記録再生方法、並びにデジタルカメラ
US20030163769A1 (en) * 2002-02-27 2003-08-28 Sun Microsystems, Inc. Memory module including an error detection mechanism for address and control signals
US6941493B2 (en) * 2002-02-27 2005-09-06 Sun Microsystems, Inc. Memory subsystem including an error detection mechanism for address and control signals
US6981079B2 (en) 2002-03-21 2005-12-27 International Business Machines Corporation Critical datapath error handling in a multiprocessor architecture
US20030191978A1 (en) * 2002-04-04 2003-10-09 International Business Machines Corporation Multiple fault location in a series of devices
US6920587B2 (en) * 2002-04-25 2005-07-19 International Business Machines Corporation Handling multiple operating system capabilities in a logical partition data processing system
US6996766B2 (en) * 2002-06-28 2006-02-07 Sun Microsystems, Inc. Error detection/correction code which detects and corrects a first failing component and optionally a second failing component
US6973613B2 (en) * 2002-06-28 2005-12-06 Sun Microsystems, Inc. Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure
US6976194B2 (en) * 2002-06-28 2005-12-13 Sun Microsystems, Inc. Memory/Transmission medium failure handling controller and method
US6996686B2 (en) * 2002-12-23 2006-02-07 Sun Microsystems, Inc. Memory subsystem including memory modules having multiple banks
US7779285B2 (en) * 2003-02-18 2010-08-17 Oracle America, Inc. Memory system including independent isolated power for each memory module
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US20040237001A1 (en) * 2003-05-21 2004-11-25 Sun Microsystems, Inc. Memory integrated circuit including an error detection mechanism for detecting errors in address and control signals
US20050015672A1 (en) * 2003-06-25 2005-01-20 Koichi Yamada Identifying affected program threads and enabling error containment and recovery
US7530008B2 (en) * 2003-08-08 2009-05-05 Sun Microsystems, Inc. Scalable-chip-correct ECC scheme
US7188296B1 (en) 2003-10-30 2007-03-06 Sun Microsystems, Inc. ECC for component failures using Galois fields
JP4622238B2 (ja) * 2003-11-19 2011-02-02 富士ゼロックス株式会社 画像形成装置
US7793229B1 (en) * 2003-12-19 2010-09-07 Unisys Corporation Recording relevant information in a GUI window of a panel dump browser tool
CN100549986C (zh) * 2005-03-24 2009-10-14 富士通株式会社 信息处理装置
KR100922409B1 (ko) * 2005-03-24 2009-10-16 후지쯔 가부시끼가이샤 정보 처리 장치 및 메모리 이상 감시 방법
US20060277444A1 (en) * 2005-06-03 2006-12-07 Nicholas Holian Recordation of error information
US20070088988A1 (en) 2005-10-14 2007-04-19 Dell Products L.P. System and method for logging recoverable errors
US9544196B2 (en) * 2006-09-20 2017-01-10 At&T Intellectual Property I, L.P. Methods, systems and computer program products for determining installation status of SMS packages
US7890836B2 (en) * 2006-12-14 2011-02-15 Intel Corporation Method and apparatus of cache assisted error detection and correction in memory
US7694195B2 (en) 2007-08-14 2010-04-06 Dell Products L.P. System and method for using a memory mapping function to map memory defects
US7949913B2 (en) * 2007-08-14 2011-05-24 Dell Products L.P. Method for creating a memory defect map and optimizing performance using the memory defect map
US9373362B2 (en) 2007-08-14 2016-06-21 Dell Products L.P. System and method for implementing a memory defect map
US7945815B2 (en) 2007-08-14 2011-05-17 Dell Products L.P. System and method for managing memory errors in an information handling system
US8195981B2 (en) * 2008-06-03 2012-06-05 International Business Machines Corporation Memory metadata used to handle memory errors without process termination
US7953914B2 (en) * 2008-06-03 2011-05-31 International Business Machines Corporation Clearing interrupts raised while performing operating system critical tasks
CN102467440A (zh) * 2010-11-09 2012-05-23 鸿富锦精密工业（深圳）有限公司 内存错误检测系统及方法
US8724408B2 (en) 2011-11-29 2014-05-13 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
US9124618B2 (en) * 2013-03-01 2015-09-01 Cassidian Cybersecurity Sas Process of reliability for the generation of warning messages on a network of synchronized data
TWI502601B (zh) * 2013-04-24 2015-10-01 Ind Tech Res Inst 混合式錯誤修復方法及其記憶體裝置
US9658920B1 (en) 2013-06-21 2017-05-23 Altera Corporation Method for reconfiguring an erroneous memory frame in an integrated circuit
US9778982B2 (en) 2013-12-09 2017-10-03 Hewlett Packard Enterprise Development Lp Memory erasure information in cache lines
KR102435181B1 (ko) 2015-11-16 2022-08-23 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 시스템의 동작 방법
US10061638B2 (en) * 2016-03-29 2018-08-28 International Business Machines Corporation Isolating faulty components in a clustered storage system with random redistribution of errors in data

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4255808A (en) * 1979-04-19 1981-03-10 Sperry Corporation Hard or soft cell failure differentiator
US4852100A (en) * 1986-10-17 1989-07-25 Amdahl Corporation Error detection and correction scheme for main storage unit
US5233614A (en) * 1991-01-07 1993-08-03 International Business Machines Corporation Fault mapping apparatus for memory
US5274646A (en) * 1991-04-17 1993-12-28 International Business Machines Corporation Excessive error correction control
US5245615A (en) * 1991-06-06 1993-09-14 International Business Machines Corporation Diagnostic system and interface for a personal computer
JPH0619805A (ja) * 1992-06-30 1994-01-28 Fujitsu Ltd メモリ異常箇所特定方法
US5410545A (en) * 1992-07-28 1995-04-25 Digital Equipment Corporation Long-term storage of controller performance
US5774647A (en) * 1996-05-15 1998-06-30 Hewlett-Packard Company Management of memory modules

Also Published As

Publication number Publication date
EP1000395B1 (de) 2004-12-01
WO1999005599A1 (en) 1999-02-04
US6158025A (en) 2000-12-05
EP1000395A1 (de) 2000-05-17
DE69827949T2 (de) 2005-10-27

Similar Documents

Publication Publication Date Title
DE69827949D1 (de) Gerät und verfahren um speicherfehler zu erkennen und zu berichten
BR0010896A (pt) Método e sistema para proporcionar uma cópia de uma página impressa
EP1008936A3 (de) Flash-Speichersteuerverfahren
DE69901255D1 (de) Mehrprozessorsystem brücke mit zugriffskontrollierung
KR910001514A (ko) 마이크로 프로세서 리세트 회로 및 방법과 컴퓨터 시스템
WO2007086150A1 (ja) メモリ破壊検出方法および装置
SE9704606D0 (sv) Metod vid processor, samt processor anpassad att verka enligt metoden
KR910001542A (ko) 정보 처리 장치의 비교 체크 기능 검사를 위한 시스템
ATE290238T1 (de) Verfahren und vorrichtung für speicherdata- fehlerdetektion und speichermodul-fehlerdetektion
US5136594A (en) Method and apparatus for providing bus parity
KR100249171B1 (ko) 비동기식 데이터 송수신 장치의 에러 검출 방법
DE59814280D1 (de) Verfahren zur schnellen Kommunikation in einem parallelen Computersystem und mit diesem Verfahren betriebenes paralleles Computersystem
JPS60122426A (ja) 書込みデ−タチエック方式
JPS6373437A (ja) パリテイ回路検査方式
JPH01277768A (ja) カウンタ装置
KR970022345A (ko) 마이크로프로세서보드의 검사장치
JPS5617442A (en) Parity error processing system
JPH0546487A (ja) フアイル盤誤実装検出装置
JPS62182905A (ja) 数値制御装置
JPH07152497A (ja) ディスク制御装置
JPS5578349A (en) Error detection system
KR910015987A (ko) 버스트에러 정정회로 및 방법
KR940015822A (ko) 다중 프로세서 시스템에서 메모리 모듈의 상태변화 시험방법
JPH04127343A (ja) 誤り検出回路
JPS56140735A (en) Error detecting system

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
R082 Change of representative

Ref document number: 1000395

Country of ref document: EP

Representative=s name: PATENTANWAELTE RUFF, WILHELM, BEIER, DAUSTER &, DE

R081 Change of applicant/patentee

Ref document number: 1000395

Country of ref document: EP

Owner name: VERDANT DEVELOPMENT NV L.L.C., US

Free format text: FORMER OWNER: INTERGRAPH TECHNOLOGIES COMPANY, LAS VEGAS, US

Effective date: 20120912

Ref document number: 1000395

Country of ref document: EP

Owner name: VERDANT DEVELOPMENT NV L.L.C., US

Free format text: FORMER OWNER: INTERGRAPH HARDWARE TECHNOLOGIES CO., LAS VEGAS, US

Effective date: 20120807

R082 Change of representative

Ref document number: 1000395

Country of ref document: EP

Representative=s name: DTS MUENCHEN PATENT- UND RECHTSANWAELTE, DE

Effective date: 20120912

Ref document number: 1000395

Country of ref document: EP

Representative=s name: DTS MUENCHEN PATENT- UND RECHTSANWAELTE, DE

Effective date: 20120807