SE9704606D0 - Metod vid processor, samt processor anpassad att verka enligt metoden - Google Patents

Metod vid processor, samt processor anpassad att verka enligt metoden

Info

Publication number
SE9704606D0
SE9704606D0 SE9704606A SE9704606A SE9704606D0 SE 9704606 D0 SE9704606 D0 SE 9704606D0 SE 9704606 A SE9704606 A SE 9704606A SE 9704606 A SE9704606 A SE 9704606A SE 9704606 D0 SE9704606 D0 SE 9704606D0
Authority
SE
Sweden
Prior art keywords
processor
output data
calculating
comparator
unit
Prior art date
Application number
SE9704606A
Other languages
English (en)
Other versions
SE511114C2 (sv
SE9704606L (sv
Inventor
Michael Rosendahl
Tomas Lars Jonsson
Per Anders Holmberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9704606A priority Critical patent/SE511114C2/sv
Publication of SE9704606D0 publication Critical patent/SE9704606D0/sv
Priority to DE69813018T priority patent/DE69813018T2/de
Priority to US09/207,765 priority patent/US6330701B1/en
Priority to PCT/SE1998/002267 priority patent/WO1999030235A2/en
Priority to EP98962793A priority patent/EP1038224B1/en
Priority to JP2000524727A priority patent/JP2001526422A/ja
Priority to AU17951/99A priority patent/AU1795199A/en
Publication of SE9704606L publication Critical patent/SE9704606L/sv
Publication of SE511114C2 publication Critical patent/SE511114C2/sv

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1654Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/165Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1629Error detection by comparing the output of redundant processing systems
    • G06F11/1641Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Detection And Correction Of Errors (AREA)
SE9704606A 1997-12-10 1997-12-10 Metod vid processor, samt processor anpassad att verka enligt metoden SE511114C2 (sv)

Priority Applications (7)

Application Number Priority Date Filing Date Title
SE9704606A SE511114C2 (sv) 1997-12-10 1997-12-10 Metod vid processor, samt processor anpassad att verka enligt metoden
DE69813018T DE69813018T2 (de) 1997-12-10 1998-12-09 Verfahren in bezug auf prozessoren und angepasste prozessoren die in übereinstimmung mit dem verfahren funktionieren
US09/207,765 US6330701B1 (en) 1997-12-10 1998-12-09 Method relating to processors, and processors adapted to function in accordance with the method
PCT/SE1998/002267 WO1999030235A2 (en) 1997-12-10 1998-12-09 A method relating to processors, and processors adapted to function in accordance with the method
EP98962793A EP1038224B1 (en) 1997-12-10 1998-12-09 A method relating to processors, and processors adapted to function in accordance with the method
JP2000524727A JP2001526422A (ja) 1997-12-10 1998-12-09 プロセッサに関連する方法と、その方法に基づく機能に適合したプロセッサ
AU17951/99A AU1795199A (en) 1997-12-10 1998-12-09 A method relating to processors, and processors adapted to function in accordance with the method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9704606A SE511114C2 (sv) 1997-12-10 1997-12-10 Metod vid processor, samt processor anpassad att verka enligt metoden

Publications (3)

Publication Number Publication Date
SE9704606D0 true SE9704606D0 (sv) 1997-12-10
SE9704606L SE9704606L (sv) 1999-06-11
SE511114C2 SE511114C2 (sv) 1999-08-09

Family

ID=20409337

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9704606A SE511114C2 (sv) 1997-12-10 1997-12-10 Metod vid processor, samt processor anpassad att verka enligt metoden

Country Status (7)

Country Link
US (1) US6330701B1 (sv)
EP (1) EP1038224B1 (sv)
JP (1) JP2001526422A (sv)
AU (1) AU1795199A (sv)
DE (1) DE69813018T2 (sv)
SE (1) SE511114C2 (sv)
WO (1) WO1999030235A2 (sv)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6587961B1 (en) * 1998-06-15 2003-07-01 Sun Microsystems, Inc. Multi-processor system bridge with controlled access
JP2001297039A (ja) * 2000-04-12 2001-10-26 Matsushita Electric Ind Co Ltd データ処理装置
JP4492035B2 (ja) * 2003-04-21 2010-06-30 日本電気株式会社 データ処理装置
DE10332557A1 (de) * 2003-07-11 2005-02-17 Siemens Ag Verfahren und Computersystem zum Betreiben einer sicherungstechnischen Anlage
US7761657B2 (en) * 2006-07-10 2010-07-20 Hitachi, Ltd. Storage control system, control method for storage control system, port selector, and controller
JP4461135B2 (ja) * 2006-12-25 2010-05-12 富士通株式会社 演算回路及び演算方法並びに情報処理装置
WO2009060953A1 (ja) * 2007-11-07 2009-05-14 Mitsubishi Electric Corporation 安全制御装置
US8051323B2 (en) * 2010-01-21 2011-11-01 Arm Limited Auxiliary circuit structure in a split-lock dual processor system
US8108730B2 (en) * 2010-01-21 2012-01-31 Arm Limited Debugging a multiprocessor system that switches between a locked mode and a split mode
US20110179255A1 (en) * 2010-01-21 2011-07-21 Arm Limited Data processing reset operations
US8959392B2 (en) 2010-03-23 2015-02-17 Continental Teves Ag & Co. Ohg Redundant two-processor controller and control method
WO2011117156A2 (de) * 2010-03-23 2011-09-29 Continental Teves Ag & Co. Ohg Kontrollrechnersystem, verfahren zur steuerung eines kontrollrechnersystems, sowie verwendung eines kontrollrechnersystems
EP2749298B1 (en) 2012-12-26 2016-04-06 Universidad Del Pais Vasco-Euskal Herriko Unibertsitatea A 1,4,5-TRISUBSTITUTED1,2,3-TRIAZOLE MIMETIC OF RGD and/or OGP10-14, PROCESS TO OBTAIN IT AND USES THEREOF
WO2015177927A1 (ja) * 2014-05-23 2015-11-26 株式会社日立製作所 情報処理装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228496A (en) * 1976-09-07 1980-10-14 Tandem Computers Incorporated Multiprocessor system
US4358823A (en) 1977-03-25 1982-11-09 Trw, Inc. Double redundant processor
US4345328A (en) * 1980-06-30 1982-08-17 Sperry Corporation ECC Check bit generation using through checking parity bits
JPH0833842B2 (ja) 1987-05-01 1996-03-29 株式会社日立製作所 論理演算装置
CA2032067A1 (en) 1989-12-22 1991-06-23 Douglas E. Jewett Fault-tolerant computer system with online reintegration and shutdown/restart
US5272696A (en) * 1992-01-23 1993-12-21 Northern Telecom Limited ATM plane merging filter for ATM switches and the method thereof
MX9306994A (es) * 1992-12-15 1994-06-30 Ericsson Telefon Ab L M Sistema de control de flujo para interruptores de paquete.
US5915082A (en) * 1996-06-07 1999-06-22 Lockheed Martin Corporation Error detection and fault isolation for lockstep processor systems

Also Published As

Publication number Publication date
EP1038224A2 (en) 2000-09-27
WO1999030235A2 (en) 1999-06-17
SE511114C2 (sv) 1999-08-09
AU1795199A (en) 1999-06-28
EP1038224B1 (en) 2003-04-02
JP2001526422A (ja) 2001-12-18
DE69813018D1 (de) 2003-05-08
SE9704606L (sv) 1999-06-11
DE69813018T2 (de) 2004-01-22
US6330701B1 (en) 2001-12-11
WO1999030235A3 (en) 1999-08-26

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