FR2426963A1 - Dispositif de detection de defauts pour une memoire dynamique - Google Patents

Dispositif de detection de defauts pour une memoire dynamique

Info

Publication number
FR2426963A1
FR2426963A1 FR7912891A FR7912891A FR2426963A1 FR 2426963 A1 FR2426963 A1 FR 2426963A1 FR 7912891 A FR7912891 A FR 7912891A FR 7912891 A FR7912891 A FR 7912891A FR 2426963 A1 FR2426963 A1 FR 2426963A1
Authority
FR
France
Prior art keywords
dynamic memory
detection device
fault detection
error check
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7912891A
Other languages
English (en)
Other versions
FR2426963B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of FR2426963A1 publication Critical patent/FR2426963A1/fr
Application granted granted Critical
Publication of FR2426963B1 publication Critical patent/FR2426963B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

L'invention concerne les mémoires dynamiques. Un système de mémoire dynamique comporte notamment un circuit de lecture qui, au cours de chaque opération de régénération, lit un mot appartenant au groupe de mots régénérés; et un circuit de contrôle d'erreur 225 déterminant si la partie d'information du mot lu correspond à la partie de contrôle d'erreur associée. Le circuit de contrôle engendre un signal de défaut lorsque la correspondance contrôlée n'existe pas. Applications aux ordinateurs.
FR7912891A 1978-05-25 1979-05-21 Dispositif de detection de defauts pour une memoire dynamique Granted FR2426963A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/909,367 US4183096A (en) 1978-05-25 1978-05-25 Self checking dynamic memory system

Publications (2)

Publication Number Publication Date
FR2426963A1 true FR2426963A1 (fr) 1979-12-21
FR2426963B1 FR2426963B1 (fr) 1985-03-08

Family

ID=25427121

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7912891A Granted FR2426963A1 (fr) 1978-05-25 1979-05-21 Dispositif de detection de defauts pour une memoire dynamique

Country Status (12)

Country Link
US (1) US4183096A (fr)
JP (1) JPS54154228A (fr)
AU (1) AU531591B2 (fr)
BE (1) BE876484A (fr)
CA (1) CA1107862A (fr)
DE (1) DE2921243A1 (fr)
ES (1) ES480935A1 (fr)
FR (1) FR2426963A1 (fr)
GB (1) GB2021826B (fr)
IT (1) IT1114048B (fr)
NL (1) NL7904100A (fr)
SE (1) SE438747B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019150A1 (fr) * 1979-05-15 1980-11-26 Mostek Corporation Procédé et circuit de test du fonctionnement d'un compteur interne de régénération d'une mémoire à accès sélectif

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506362A (en) * 1978-12-22 1985-03-19 Gould Inc. Systematic memory error detection and correction apparatus and method
US4360917A (en) * 1979-02-07 1982-11-23 The Warner & Swasey Company Parity fault locating means
US4241425A (en) * 1979-02-09 1980-12-23 Bell Telephone Laboratories, Incorporated Organization for dynamic random access memory
US4319356A (en) * 1979-12-19 1982-03-09 Ncr Corporation Self-correcting memory system
DE3069611D1 (en) * 1979-12-27 1984-12-13 Fujitsu Ltd Apparatus and method for testing semiconductor memory devices
US4380812A (en) * 1980-04-25 1983-04-19 Data General Corporation Refresh and error detection and correction technique for a data processing system
EP0054023A1 (fr) * 1980-06-02 1982-06-23 Mostek Corporation Memoire a semi-conducteur utilisee en association avec un circuit de detection et de correction d'erreurs
US4412314A (en) * 1980-06-02 1983-10-25 Mostek Corporation Semiconductor memory for use in conjunction with error detection and correction circuit
US4359771A (en) * 1980-07-25 1982-11-16 Honeywell Information Systems Inc. Method and apparatus for testing and verifying the operation of error control apparatus within a memory
US4369510A (en) * 1980-07-25 1983-01-18 Honeywell Information Systems Inc. Soft error rewrite control system
US4380805A (en) * 1980-09-08 1983-04-19 Mostek Corporation Tape burn-in circuit
EP0059188A1 (fr) * 1980-09-08 1982-09-08 Mostek Corporation Circuit de vieillissement accelere de bande
EP0082198A1 (fr) * 1981-06-26 1983-06-29 Ncr Corporation Dispositif de controle d'erreur de memoire a haute vitesse
US4542454A (en) * 1983-03-30 1985-09-17 Advanced Micro Devices, Inc. Apparatus for controlling access to a memory
US4612640A (en) * 1984-02-21 1986-09-16 Seeq Technology, Inc. Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
JPH0620303B2 (ja) * 1984-11-08 1994-03-16 日本電信電話株式会社 フレ−ム間符号化方式におけるリフレッシュ処理方式
CA1240066A (fr) * 1985-08-15 1988-08-02 John R. Ramsay Circuit de regeneration et de controle de parite pour memoire dynamique
JPH087995B2 (ja) * 1985-08-16 1996-01-29 富士通株式会社 ダイナミツク半導体記憶装置のリフレツシユ方法および装置
US4691303A (en) * 1985-10-31 1987-09-01 Sperry Corporation Refresh system for multi-bank semiconductor memory
US4733393A (en) * 1985-12-12 1988-03-22 Itt Corporation Test method and apparatus for cellular array processor chip
US4783782A (en) * 1985-12-12 1988-11-08 Alcatel U.S.A. Corporation Manufacturing test data storage apparatus for dynamically reconfigurable cellular array processor chip
US6760881B2 (en) 2001-10-16 2004-07-06 International Business Machines Corporation Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)
FR2851862B1 (fr) * 2003-02-27 2006-12-29 Radiotelephone Sfr Procede de generation d'une permutation pseudo-aleatoire d'un mot comportant n digits
US7752427B2 (en) * 2005-12-09 2010-07-06 Atmel Corporation Stack underflow debug with sticky base
US20080080284A1 (en) * 2006-09-15 2008-04-03 Peter Mayer Method and apparatus for refreshing memory cells of a memory
US8621324B2 (en) * 2010-12-10 2013-12-31 Qualcomm Incorporated Embedded DRAM having low power self-correction capability
US9583219B2 (en) 2014-09-27 2017-02-28 Qualcomm Incorporated Method and apparatus for in-system repair of memory in burst refresh
JP7016332B2 (ja) * 2019-07-05 2022-02-04 華邦電子股▲ふん▼有限公司 半導体メモリ装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3944800A (en) * 1975-08-04 1976-03-16 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1197418A (en) * 1969-02-05 1970-07-01 Ibm Data Storage Apparatus
US3801964A (en) * 1972-02-24 1974-04-02 Advanced Memory Sys Inc Semiconductor memory with address decoding
US3814922A (en) * 1972-12-01 1974-06-04 Honeywell Inf Systems Availability and diagnostic apparatus for memory modules

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3944800A (en) * 1975-08-04 1976-03-16 Bell Telephone Laboratories, Incorporated Memory diagnostic arrangement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/75 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0019150A1 (fr) * 1979-05-15 1980-11-26 Mostek Corporation Procédé et circuit de test du fonctionnement d'un compteur interne de régénération d'une mémoire à accès sélectif

Also Published As

Publication number Publication date
DE2921243A1 (de) 1979-11-29
ES480935A1 (es) 1980-01-16
JPS54154228A (en) 1979-12-05
AU4724579A (en) 1979-11-29
AU531591B2 (en) 1983-09-01
CA1107862A (fr) 1981-08-25
SE7904350L (sv) 1979-11-26
GB2021826B (en) 1982-09-22
BE876484A (fr) 1979-09-17
IT1114048B (it) 1986-01-27
IT7922960A0 (it) 1979-05-24
SE438747B (sv) 1985-04-29
NL7904100A (nl) 1979-11-27
FR2426963B1 (fr) 1985-03-08
US4183096A (en) 1980-01-08
DE2921243C2 (fr) 1987-06-25
GB2021826A (en) 1979-12-05

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Legal Events

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