DE69823601D1 - Hierarchische Spaltenleitungsauswahl für Multi-Bank-DRAM-Speicher und Verfahren dazu - Google Patents

Hierarchische Spaltenleitungsauswahl für Multi-Bank-DRAM-Speicher und Verfahren dazu

Info

Publication number
DE69823601D1
DE69823601D1 DE69823601T DE69823601T DE69823601D1 DE 69823601 D1 DE69823601 D1 DE 69823601D1 DE 69823601 T DE69823601 T DE 69823601T DE 69823601 T DE69823601 T DE 69823601T DE 69823601 D1 DE69823601 D1 DE 69823601D1
Authority
DE
Germany
Prior art keywords
method therefor
line selection
column line
dram memory
bank dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69823601T
Other languages
English (en)
Other versions
DE69823601T2 (de
Inventor
Toshiaki Kirihata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/927,160 external-priority patent/US5949732A/en
Priority claimed from US08/927,158 external-priority patent/US5822268A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69823601D1 publication Critical patent/DE69823601D1/de
Application granted granted Critical
Publication of DE69823601T2 publication Critical patent/DE69823601T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
DE69823601T 1997-09-11 1998-08-24 Hierarchische Spaltenleitungsauswahl für Multi-Bank-DRAM-Speicher und Verfahren dazu Expired - Fee Related DE69823601T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/927,160 US5949732A (en) 1997-09-11 1997-09-11 Method of structuring a multi-bank DRAM into a hierarchical column select line architecture
US08/927,158 US5822268A (en) 1997-09-11 1997-09-11 Hierarchical column select line architecture for multi-bank DRAMs
US927160 1997-09-11
US927158 2004-08-27

Publications (2)

Publication Number Publication Date
DE69823601D1 true DE69823601D1 (de) 2004-06-09
DE69823601T2 DE69823601T2 (de) 2006-03-23

Family

ID=27129937

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69823601T Expired - Fee Related DE69823601T2 (de) 1997-09-11 1998-08-24 Hierarchische Spaltenleitungsauswahl für Multi-Bank-DRAM-Speicher und Verfahren dazu

Country Status (4)

Country Link
EP (1) EP0902434B1 (de)
JP (1) JP3229267B2 (de)
KR (1) KR100305937B1 (de)
DE (1) DE69823601T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020000965A (ko) * 2000-06-23 2002-01-09 신영주 안전밸브
US6714467B2 (en) * 2002-03-19 2004-03-30 Broadcom Corporation Block redundancy implementation in heirarchical RAM's
JP2002230968A (ja) 2001-02-02 2002-08-16 Mitsubishi Electric Corp 半導体記憶装置
US6480424B1 (en) * 2001-07-12 2002-11-12 Broadcom Corporation Compact analog-multiplexed global sense amplifier for RAMS
DE10339665B3 (de) * 2003-08-28 2005-01-13 Infineon Technologies Ag Halbleiter-Speicherbauelement, mit Steuereinrichtung zum Aktivieren von Speicherzellen und Verfahren zum Betrieb eines Halbleiter-Speicherbauelements
JP2006134469A (ja) 2004-11-05 2006-05-25 Elpida Memory Inc 半導体記憶装置
KR100855572B1 (ko) 2007-04-04 2008-09-01 삼성전자주식회사 반도체 메모리 장치에서의 비트라인 센스앰프의레이아웃구조

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0772991B2 (ja) * 1988-12-06 1995-08-02 三菱電機株式会社 半導体記憶装置
JPH0814985B2 (ja) * 1989-06-06 1996-02-14 富士通株式会社 半導体記憶装置
JPH08221981A (ja) * 1994-12-15 1996-08-30 Mitsubishi Electric Corp 同期型半導体記憶装置

Also Published As

Publication number Publication date
EP0902434B1 (de) 2004-05-06
EP0902434A3 (de) 1999-12-08
KR19990029677A (ko) 1999-04-26
EP0902434A2 (de) 1999-03-17
KR100305937B1 (ko) 2001-10-19
JP3229267B2 (ja) 2001-11-19
DE69823601T2 (de) 2006-03-23
JPH11126477A (ja) 1999-05-11

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication of lapse of patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee