DE69624712T2 - Verfahren zur herstellung einer metall-leitungsstruktur für eine integrierte schaltung mit verbessertem elektromigrationswiderstand - Google Patents

Verfahren zur herstellung einer metall-leitungsstruktur für eine integrierte schaltung mit verbessertem elektromigrationswiderstand

Info

Publication number
DE69624712T2
DE69624712T2 DE69624712T DE69624712T DE69624712T2 DE 69624712 T2 DE69624712 T2 DE 69624712T2 DE 69624712 T DE69624712 T DE 69624712T DE 69624712 T DE69624712 T DE 69624712T DE 69624712 T2 DE69624712 T2 DE 69624712T2
Authority
DE
Germany
Prior art keywords
layer
silicon
deposited
depositing
aluminum alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69624712T
Other languages
German (de)
English (en)
Other versions
DE69624712D1 (de
Inventor
Bill Klaasen
Paul Lee
Darryl Restaino
M. Vollmer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE69624712D1 publication Critical patent/DE69624712D1/de
Publication of DE69624712T2 publication Critical patent/DE69624712T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69624712T 1995-08-10 1996-08-01 Verfahren zur herstellung einer metall-leitungsstruktur für eine integrierte schaltung mit verbessertem elektromigrationswiderstand Expired - Lifetime DE69624712T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/513,494 US5641992A (en) 1995-08-10 1995-08-10 Metal interconnect structure for an integrated circuit with improved electromigration reliability
PCT/US1996/012603 WO1997006562A1 (en) 1995-08-10 1996-08-01 Metal interconnect structure for an integrated circuit with improved electromigration reliability

Publications (2)

Publication Number Publication Date
DE69624712D1 DE69624712D1 (de) 2002-12-12
DE69624712T2 true DE69624712T2 (de) 2003-09-11

Family

ID=24043525

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69624712T Expired - Lifetime DE69624712T2 (de) 1995-08-10 1996-08-01 Verfahren zur herstellung einer metall-leitungsstruktur für eine integrierte schaltung mit verbessertem elektromigrationswiderstand

Country Status (6)

Country Link
US (2) US5641992A (enExample)
EP (1) EP0843895B1 (enExample)
JP (1) JP2000501882A (enExample)
KR (1) KR19990036191A (enExample)
DE (1) DE69624712T2 (enExample)
WO (1) WO1997006562A1 (enExample)

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JPH09115829A (ja) * 1995-10-17 1997-05-02 Nissan Motor Co Ltd アルミニウム配線部を有する半導体装置およびその製造方法
US5994217A (en) * 1996-12-16 1999-11-30 Chartered Semiconductor Manufacturing Ltd. Post metallization stress relief annealing heat treatment for ARC TiN over aluminum layers
US5943601A (en) * 1997-04-30 1999-08-24 International Business Machines Corporation Process for fabricating a metallization structure
US5891802A (en) * 1997-07-23 1999-04-06 Advanced Micro Devices, Inc. Method for fabricating a metallization stack structure to improve electromigration resistance and keep low resistivity of ULSI interconnects
US5942799A (en) * 1997-11-20 1999-08-24 Novellus Systems, Inc. Multilayer diffusion barriers
KR100249047B1 (ko) * 1997-12-12 2000-03-15 윤종용 반도체 소자 및 그 제조 방법
FR2774811B1 (fr) * 1998-02-10 2003-05-09 Sgs Thomson Microelectronics Procede de formation de lignes conductrices sur des circuits integres
US5994219A (en) * 1998-06-04 1999-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Add one process step to control the SI distribution of Alsicu to improved metal residue process window
TW439204B (en) * 1998-09-18 2001-06-07 Ibm Improved-reliability damascene interconnects and process of manufacture
JP2000150520A (ja) * 1998-11-10 2000-05-30 Internatl Business Mach Corp <Ibm> 相互接続部、及び相互接続部の製造方法
US6777810B2 (en) * 1999-02-19 2004-08-17 Intel Corporation Interconnection alloy for integrated circuits
US6352620B2 (en) 1999-06-28 2002-03-05 Applied Materials, Inc. Staged aluminum deposition process for filling vias
US6433429B1 (en) * 1999-09-01 2002-08-13 International Business Machines Corporation Copper conductive line with redundant liner and method of making
US6534404B1 (en) 1999-11-24 2003-03-18 Novellus Systems, Inc. Method of depositing diffusion barrier for copper interconnect in integrated circuit
US7179743B2 (en) 2003-01-20 2007-02-20 Systems On Silicon Manufacturing Company Pte. Ltd. Titanium underlayer for lines in semiconductor devices
JP2004266039A (ja) * 2003-02-28 2004-09-24 Shin Etsu Handotai Co Ltd 発光素子及び発光素子の製造方法
US20040207093A1 (en) * 2003-04-17 2004-10-21 Sey-Shing Sun Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnects
US6882924B2 (en) * 2003-05-05 2005-04-19 Precision Engine Controls Corp. Valve flow control system and method
US7096450B2 (en) 2003-06-28 2006-08-22 International Business Machines Corporation Enhancement of performance of a conductive wire in a multilayered substrate
KR100536808B1 (ko) * 2004-06-09 2005-12-14 동부아남반도체 주식회사 반도체 소자 및 그 제조 방법
US7339274B2 (en) * 2004-08-17 2008-03-04 Agere Systems Inc. Metallization performance in electronic devices
US20070144892A1 (en) * 2005-12-26 2007-06-28 Hui-Shen Shih Method for forming metal film or stacked layer including metal film with reduced surface roughness
US20090120785A1 (en) * 2005-12-26 2009-05-14 United Microelectronics Corp. Method for forming metal film or stacked layer including metal film with reduced surface roughness
KR100650904B1 (ko) * 2005-12-29 2006-11-28 동부일렉트로닉스 주식회사 알루미늄 배선 형성 방법
US8003536B2 (en) * 2009-03-18 2011-08-23 International Business Machines Corporation Electromigration resistant aluminum-based metal interconnect structure
CN102157356B (zh) * 2011-03-15 2015-10-07 上海华虹宏力半导体制造有限公司 金属-绝缘体-金属半导体器件的下电极的制备方法
US9851506B2 (en) * 2015-06-04 2017-12-26 Elenion Technologies, Llc Back end of line process integrated optical device fabrication

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US3879840A (en) * 1969-01-15 1975-04-29 Ibm Copper doped aluminum conductive stripes and method therefor
US4926237A (en) * 1988-04-04 1990-05-15 Motorola, Inc. Device metallization, device and method
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
US5658828A (en) * 1989-11-30 1997-08-19 Sgs-Thomson Microelectronics, Inc. Method for forming an aluminum contact through an insulating layer
US5478780A (en) * 1990-03-30 1995-12-26 Siemens Aktiengesellschaft Method and apparatus for producing conductive layers or structures for VLSI circuits
JPH04116821A (ja) * 1990-09-06 1992-04-17 Fujitsu Ltd 半導体装置の製造方法
KR960001601B1 (ko) * 1992-01-23 1996-02-02 삼성전자주식회사 반도체 장치의 접촉구 매몰방법 및 구조
KR920010620A (ko) * 1990-11-30 1992-06-26 원본미기재 다층 상호접속선을 위한 알루미늄 적층 접점/통로 형성방법
US5345108A (en) * 1991-02-26 1994-09-06 Nec Corporation Semiconductor device having multi-layer electrode wiring
DE4200809C2 (de) * 1991-03-20 1996-12-12 Samsung Electronics Co Ltd Verfahren zur Bildung einer metallischen Verdrahtungsschicht in einem Halbleiterbauelement
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same
JP2811131B2 (ja) * 1991-04-26 1998-10-15 三菱電機株式会社 半導体装置の配線接続構造およびその製造方法
EP0525517A1 (de) * 1991-08-02 1993-02-03 Siemens Aktiengesellschaft Verfahren zur Auffüllung mindestens eines Kontaktloches in einer isolierenden Schicht
JPH0590203A (ja) * 1991-09-27 1993-04-09 Nec Corp 半導体装置の製造方法
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JPH0786401A (ja) * 1993-09-17 1995-03-31 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
WO1997006562A1 (en) 1997-02-20
US5641992A (en) 1997-06-24
JP2000501882A (ja) 2000-02-15
DE69624712D1 (de) 2002-12-12
EP0843895A1 (en) 1998-05-27
KR19990036191A (ko) 1999-05-25
US5798301A (en) 1998-08-25
EP0843895B1 (en) 2002-11-06

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: INFINEON TECHNOLOGIES AG, 81669 MUENCHEN, DE

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK, N.Y

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

Owner name: QIMONDA AG, 81739 MUENCHEN, DE