Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76841—Barrier, adhesion or liner layers
  • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
  • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
  • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L23/53204—Conductive materials
  • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
  • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
  • H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• the present invention relates generally to the interconnect structures contained within an integrated circuit device. More particularly, the present invention relates to a -multilayer interconnect structure that uses layers of titanium, titanium nitride and aluminum-copper alloy to improve electromigration reliability.
• Integrated circuits generally comprise a semiconductor substrate upon which are formed various electronic components such as transistors, diodes and the like.
• Interconnect layers are formed on the semiconductor substrate to electrically interconnect the various electronic components to each other and to external components.
• the interconnect layers used on the semiconductor substrate have been made from polysilicon films, high temperature metal films, metal silicide films, aluminum films and aluminum alloy films.
• Each of these interconnect layers have an inherent resistance.
• the performance characteristics of highly integrated, high speed integrated circuits require that the resistance within the interconnect layers be held to a minimum.
• high speed integrated circuits typically use interconnect structures made of aluminum films or aluminum alloy films that have a relatively small resistivity as compared to the other interconnect structure choices.
• Patent No. 5,278,099 to Maeda entitled METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING WIRING ELECTRODES
• U.S. Patent No. 5,313,101 to Harada et al. entitled INTERCONNECT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE.
• TiN titanium nitride
• barrier films have been used, electromigration still occurs between the aluminum alloy interconnect structure and the underlying silicon-based semiconductor substrate. In order to limit the amount of electromigration induced failure in an integrated circuit, the current density is limited within the interconnect structures.
• an objective of the present invention to provide an interconnect structure for an integrated circuit that prevents alloy spiking of the below lying substrate and has greatly improved electromigration reliability, thereby enabling integrated circuits that are more reliable, have higher performance rates and have increased chip density.
• the present invention is a multilayer interconnect structure for a semiconductor integrated circuit comprising a base layer -of titanium, a second layer of titanium nitride, a third layer of an aluminum alloy and a top layer of titanium nitride. All of the layers contained within the multilayer interconnect structure are deposited by in- situ deposition in an ultra-high vacuum deposition system. The different layers deposited in the deposition system are conducted consecutively without a disruption to the vacuum. Although each layer in the multilayer interconnect structure are deposited within the integrated ultra-high vacuum deposition system, with multiple deposition chambers, the deposition of the different layers is conducted at different temperatures.
• the time to the electromigration failure of the multilayer interconnect structure, caused by the electromigration of the aluminum alloy, is greatly increased by depositing the aluminum alloy layer at a temperature in excess of 300°C and preferably between 350°C and 550°C.
• the titanium layer and the adjacent titanium nitride layer below the aluminum alloy layer provide the interconnect structure with low resistivity and prevent alloy spiking of the base substrate.
• a multilayer interconnect structure is provided that has improved electromigration reliability and a low resistance, thereby enabling more dense applications within an integrated circuit.
• Fig. 1 is a cross-sectional view of a segment of a integrated circuit formed on a silicon-based substrate, containing a preferred embodiment of the present invention multilayer interconnect structure;
• Fig. 2 is a cross-sectional view of the silicon-based substrate upon which the present invention multilayer interconnect structure is deposited;
• Fig. 3 is a cross-sectional view of the first titanium layer of the present invention interconnect structure deposited on the silicon-based substrate of Fig. 2;
• Fig. 4 is a cross-sectional view of the second titanium nitride layer of the present invention interconnect structure deposited on the titanium layer of Fig. 3;
• Fig. 5 is a cross-sectional view of the third aluminum alloy layer of the present invention interconnect structure deposited on the second titanium nitride layer of Fig. 4;
• Fig. 6 is a cross-sectional view of the forth titanium layer of the present invention interconnect structure deposited on the third aluminum alloy layer of Fig. 5.
• the present invention is a multilayer interconnect structure for use within an integrated circuit.
• an exemplary embodiment of the present invention multilayer interconnect structure 10 is shown as part of an integrated circuit segment 12.
• the integrated circuit segment 12 includes a silicon-based substrate 14 upon which are disposed doped regions 16.
• An insulating oxide film 18 is deposited over the silicon-based substrate 14 leaving the doped regions 16 exposed.
• the multilayer interconnect structures 10 are deposited over the insulating oxide layer 18 and the exposed doped regions 16 of the silicon-based substrate 14.
• the multilayer interconnect structure 10 is comprised of a layer of titanium (Ti) 20, a layer of titanium nitride (TiN) 22, a layer of aluminum copper alloy 24 and a top layer of titanium nitride 26.
• the multilayer interconnect structures 10 are isolated from each other by a second oxide layer 28. Segments of a metal contact layer 32 extend through the second oxide layer 28 and contact the multilayer interconnect structures 10, thereby providing a means for electrically coupling the multilayer interconnect structures 10 to external components.
• a silicon-based semiconductor substrate 14 is provided.
• the silicon-based substrate is selectively doped by conventional methods creating the doped regions 16.
• the doped regions 16 may be formed as part of a transistor structure or any other integrated component.
• An oxide layer 18 is deposited onto the silicon-based substrate 14 using tradition deposition techniques. The oxide layer 18 is selectively etched, thereby exposing the doped regions 16 on the silicon-based substrate 14.
• the silicon- based substrate 14 is placed within a clustered ultra-high vacuum (UHV) deposition system.
• UHV ultra-high vacuum
• the UHV deposition chamber 30 is evacuated to an ultra high vacuum where the pressure of oxygen and other reactive impurity gases within the UHV deposition chamber are reduced to below 10 "6 Pa.
• the silicon-based substrate 14 and oxide layer 18 are heated and cleaned of impurities within the UHV deposition chamber 30.
• a layer of titanium 20, approximately 250A thick is deposited in-situ over the oxide layer 18 and the exposed doped regions 16.
• the Ti layer 20 is deposited at a temperature between 150°C and 300°C.
• TiN layer 22- is deposited in-situ within the same UHV deposition chamber 30 without release of the vacuum between the Ti deposition and the TiN deposition.
• the TiN layer 22 is preferably deposited at between 150°C and 350°C.
• a layer of aluminum alloy 24 is deposited over the TiN layer 22.
• the aluminum alloy layer 24 is Al-0.5% Cu.
• the aluminum alloy layer 24 is deposited at a thickness of approximately 1 ⁇ m, and deposition is conducted at a high temperature.
• the deposition of the aluminum alloy layer 24 is performed in the UHV deposition chamber 30 with no release of the ultra high vacuum between the TiN deposition and the aluminum alloy deposition.
• the aluminum alloy deposition is preferably performed at the highest temperature possible, given the temperature tolerances of the substrate 14, oxide layer 18, Ti layer 20 and TiN layer 22.
• the deposition temperature should be at least 350°C but preferably deposition should be performed near or about 550 ⁇ C.
• a TiN antireflection layer 26 is deposited over the aluminum alloy layer 24, thereby completing the four layers of the interconnect structure 10.
• the TiN antireflection layer 26 is deposited in the same UHV deposition chamber 30 as are the other layers of the interconnect structure 10, without a release of the ultra high vacuum. Since the TiN layer 22 below the aluminum alloy layer 24 has already been deposited, the deposition source and targets already exist within the UHV deposition chamber 30 to deposit the TiN antireflection layer 26. This reduces the complexity and cost associated with manufacturing the overall interconnect structure 10.
• the Ti layer 20 is provided to function as a barrier metal layer between the aluminum alloy layer 24 and the silicon-based substrate 14.
• the Ti layer 20 alone while being a superior contact material in achieving a low resistance ohmic contact, does not act as a complete barrier to alloy spikes. If the Ti layer 20 alone were provided between the silicon-based substrate 14 and aluminum alloy layer 24, the titanium would react simultaneously with the silicon and the aluminum, so that alloy spikes into the silicon-based substrate eventually would occur. It is for this reason that the TiN layer 22 is provided between the Ti layer 20 and the aluminum alloy layer 24.
• the TiN layer 22 acts as a barrier metal to block aluminum diffusion along the grain boundaries in the aluminum alloy layer 24, thus preventing the growth of alloy spikes.
• the Ti layer 20 and the TiN layer 22 have a high resistance to electromigration and will constitute a current path even if the aluminum alloy layer 24 were to fail due to electromigration. As a result, a complete failure of the overall multilayer interconnect structure 10 is prevented.
• the in-situ deposition of the Ti layer 20, TiN layer 22 and aluminum alloy layer 24 in an uninterrupted UHV deposition chamber in combination with the high temperature deposition of the aluminum alloy layer 24 results in an improved electromigration life of up to four times that of prior art interconnect structures that also use titanium based boundary layers.
• Tables I and II seven different interconnect structures are tested in comparison with the four layer interconnect structure of the present invention. In both tables, the present invention is represented by test sample #7. TABLE I
• electromigration lifetime (ELT) and sigma of the electromigration fail distribution are summarized for the seven test samples set forth in Table I.
• the test structures consist of Ml tungsten cap aluminum line, tapered vias (only one size allowed) , and a RIE M2 line.
• the electromigration test structure is designed to void the M2 near the Via 2, simulating the weakest point in normal product design.
• the electromigration life time (ELT) of the present invention interconnect structure is between two times and four times as long as the other samples tested.
• ELT electromigration life time
• the prior art does use Ti/TiN/aluminum alloy interconnect structures, the prior art does not deposit the aluminum alloy with in-situ UHV deposition at temperatures in excess of 300°C. Rather the prior art is more indicative of test sample #6, wherein Ti/TiN/aluminum alloy is deposited at low temperatures using traditional deposition techniques.
• the present invention test sample still has an ELT of between two times and four times greater than the other samples even though the same base materials are used.
• interconnect structure 10 is deposited, the interconnect structure 10 is etched and covered with an insulating second oxide layer 28. The second oxide layer 28 is then etched in the areas above where the interconnect structure 10 is to be engaged. A metal contact layer 32 is deposited upon the second oxide layer 28 and the exposed region of the interconnect structure 10. The metal contact layer 32 is then selectively etched, providing external contacts for coupling the underlying interconnect structure 10 to external components. Since the first TiN layer 22 under the aluminum alloy layer 24 has a thickness sufficient to prevent the growth of alloy spikes, the aluminum alloy layer 24 need not contain silicon. As a result, silicon does not precipitate in the metal contact layer 32 and the problems of silicon precipitation are avoided.

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• 1995
  • 1995-08-10 US US08/513,494 patent/US5641992A/en not_active Expired - Lifetime
• 1996
  • 1996-08-01 KR KR1019980700859A patent/KR19990036191A/ko not_active Ceased
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