US20030022480A1

US20030022480A1 - Method of doping copper metallization

Info

Publication number: US20030022480A1
Application number: US10/253,691
Authority: US
Inventors: Ming-Hsing Tsai; Sheng-Hsiang Chen
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 1999-10-04
Filing date: 2002-09-24
Publication date: 2003-01-30
Also published as: US6479389B1

Abstract

This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed by a chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a layer of pure copper. In the second embodiment of this invention chemical vapor deposition (CVD) or electrochemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film. In yet another embodiment to these methods, special, separate low temperature annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.

Description

BACKGROUND OF THE INVENTION

(1) Field of the Invention

It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper alloy films are formed by a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electrochemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.

As a background to the current invention, the requirement of lower resistance material has been more stringent as the device dimensions approach micron and sub-micron design ground rules. Pure copper metal lines have been one of the best choices because of copper's low resistivity and high conductivity. However, pure copper films are easily oxidized. Alloying copper with other elements, such as, Zr, Al, Ti, Sn, Zn, Mg aides in preventing copper oxidation/corrosion, by forming a dense passivating oxide on the copper surface. Furthermore, alloying of copper will improve the electromigration (EM) resistance of copper, due to a reduction in grain boundary diffusion.

This invention describes the formation of special copper alloy films by using a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.

(2) Description of Related Art

The present invention is a new and improved method for fabricating special copper alloy films by using a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys. High conductivity, low resistivity conducting metal lines are important in fabricating quarter micron and below semiconductor devices. The related Prior Art background patents will now be described in this section.

U.S. Pat. No. 5,891,804 entitled “Process for Conductors with Selective Deposition”, granted Apr. 6, 1999 to Havemann and Stuitz shows a copper seed layer and a copper layer there over. This is a method of forming a conductor on an interlevel dielectric layer which is over an electronic microcircuit substrate, and the structure produced thereby. The method utilizes: forming an interlevel dielectric layer over the interlevel dielectric layer; forming a conductor groove in the intralevel dielectric layer exposing a portion of the interlevel dielectric layer; anisotropically depositing a selective deposition initiator onto the intralevel dielectric layer and onto the exposed portion of the interlevel dielectric layer; and selectively depositing conductor metal to fill the groove to at least half-full. The selective deposition initiator may be selected from the group consisting of tungsten, titanium, palladium, platinum, copper, aluminum, and combinations thereof. In one embodiment, the selective deposition initiator is palladium, and the selectively deposited conductor metal is principally copper.

U.S. Pat. No. 5,891,802 entitled “Method for Fabricating a Metallization Stack Structure to Improve Electromigration Resistance and Keep Low Resistivity of ULSI Interconnects” granted Apr. 6, 1999 to Tao and Fang shows a pure copper layer sandwiched between two doped copper layers. There is described a metallization stack structure and a method for fabricating the same so as to produce a higher electromigration resistance and yet maintain a relatively low resistivity. The metallization stack structure includes a pure copper layer sandwiched between a top thin doped copper layer and a bottom thin doped copper layer. The top and bottom thin doped copper layers produce a higher electromigration resistance. The pure copper layer produces a relatively low resistivity. Note, doped copper layers increase line resistance and therefore must be thin contributing only a small cross-section of the conducting line.

U.S. Pat. No. 5,719,447 entitled “Metal Alloy Interconnections for Integrated Circuits” granted Feb. 17, 1998 to Gardner shows a barrier layer, and a physical vapor deposited (PVD) sputtered copper alloy layer. The metal-alloy interconnects of this invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3 micro-Ohm-cm

The present invention is directed to a novel and improved method of fabrication an integrated circuit, in which special copper alloy films are formed by a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electrochemical deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper alloy films are formed by combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electrochemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys.

Prior Art methods provide the following consisting of: a semiconductor silicon substrate with the, first level of metal copper wiring being defined, embedded in the first layer of insulator, silicon oxide SiO _x. The invention starts with these conventional layers being provided by Prior Art methods, in addition, to patterned and etched via holes and trenches (channels) in deposited insulating material. Also provided by Prior Art methods, can be a metal “seed layer” and metal diffusion barrier layer beneath the metal copper wiring layers. To obtain adequate liner coverage using collimated reactive sputtered, physical vapor deposition (PVD), TaN, Ti/TiN, TiN, WN liners (diffusion barrier) and seed layers, a larger liner thickness must be applied.

Copper alloys have been found to be of advantage in the prevention of oxidation of copper and improving electromigration (EM) resistance of copper films. However, the primary method of forming copper alloys is by physical vapor deposition (PVD), a sputtering method which uses a sputtering target composed of the copper alloy. The copper films deposited from PVD methods have poor conformality and are not applicable for good planar gap fill properties. However, chemical vapor deposition (CVD) or electrochemical deposition (ECD) of pure copper can fill high aspect ratio vias and trenches. Note, for chemical vapor deposition (CVD) or electro-chemical deposition (ECD), only pure copper films can be deposited. This invention describes two new methods to form copper alloy films, copper alloying with, e.g., Zr, Al, Ti, Sn, Zn, Mg.

In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, i.e., Zr, Al, Ti, Sn, Zn, Mg, is then followed by a chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a layer of pure copper.

In the second embodiment of this invention chemical vapor deposition (CVD) or electro-chemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film, e.g., doped with Zr, Al, Ti, Sn, Zn, Mg.

In yet another embodiment to these methods, special, separate annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.

Note, elements which easily form metal alloys with copper, face centered cubic crystal structure (fcc), in a solid state solution, are those which possess the following properties: crystal structure the same or close to face centered cubic (fcc) of copper, the same or close to the atomic packing of copper, close in atomic size to metallic copper, (also close in ionic size and close in valence to copper).

The final process steps are chemical mechanical polish (CMP) of excess conducting metal, in a manner to form conducting lines and vias without dishing.

In summary, some of the advantages of this invention for alloying copper layers are firstly, the prevention of copper oxidation/corrosion by the forming a protective, passivating stable oxide. Enhanced electromigration (EM) resistance by hindering grain boundary (fast) diffusion, while still maintaining low resistivity (low sheet rho for conducting line) and high conductivity. Improved copper to silicon nitride and silicon dioxide adhesion. Prevention of hillock formation of copper, especially during deposition processes, i.e., copper sputtering. Finally, the key advantage of this invention, combining the deposition techniques of good planar via fill and conformality properties of both chemical vapor deposition (CVD) and electro-chemical deposition with physical vapor deposition (PVD) sputtering for doping of copper alloy.

This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the “DESCRIPTION OF THE PREFERRED EMBODIMENTS” section.

BRIEF DESCRIPTION OF THE DRAWINGS

The object and other advantages of this invention are best described in the preferred embodiments with reference to the attached drawings that include: [0021]
FIG. 1[0022] a, which in cross-sectional representation illustrates the initial starting point for the first embodiment of this invention, deposition of a seed layer and physical vapor deposition (PVD) sputtering of a copper alloy layer.
FIG. 1[0023] b, which in cross-sectional representation illustrates one key process step of this invention, the chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a planar thick layer of pure copper.
FIG. 1[0024] c, which in cross-sectional representation illustrates another key process step of this invention, the annealing of the copper layers to form copper alloys.
FIG. 2[0025] a, which in cross-sectional representation illustrates the initial starting point for the second embodiment of this invention, deposition of a seed layer and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a planar thick layer of pure copper.
Fig. 2[0026] b, which in cross-sectional representation illustrates one key process step of this invention, the physical vapor deposition (PVD) sputtering of a copper alloy layer.
FIG. 2[0027] c, which in cross-sectional representation illustrates another key process step of this invention, the annealing of the copper layers to form copper alloys.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper alloy films are formed by a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD) or electro-chemical deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper corrosion/oxidation and electromigration resistant alloys. [0028]
Copper alloys have been found to be of advantage in the prevention of oxidation of copper and improving electromigration (EM) resistance of copper films. However, the method of forming copper alloys is primarily by physical vapor deposit (PVD), a sputtering method which has uses a sputtering target composed of the copper alloy. The copper films deposited from PVD methods have poor conformality and are not applicable for good gap fill properties. Chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of pure copper can fill high aspect ratio vias and trenches. Note that for chemical vapor deposition (CVD) or electro-chemical deposition (ECD), only pure copper films can be deposited. This invention describes two new methods to form copper alloy films, which consists of combination of the above processes. [0029]
Referring FIG. 1[0030] a, which in cross-sectional representation, sketches the starting point for the first embodiment of this invention. As a background, provided by Prior Art methods are the following: a semiconductor silicon substrate 10 with the first level of metal copper wiring 11 being defined, embedded in the first layer of insulator 12, silicon oxide SiO_x. The invention starts with these conventional layers being provided by Prior Art methods, in addition, to patterned and etched via holes (not shown in Figs.) and trenches (channels) 13 in deposited insulating material 14. A metal “seed layer” and metal diffusion barrier layer beneath the metal copper wiring layers is deposited (too thin, not shown in Figs.). To obtain adequate liner coverage using collimated reactive sputtered, physical vapor deposition (PVD), TaN, Ti/TiN, TiN, WN liners (diffusion barrier) and seed layers, a larger liner thickness must be applied.
Referring again to FIG. 1[0031] a, which in cross-sectional representation illustrates the first embodiment of this invention which is the physical vapor deposition (PVD) or sputtering of a copper alloy film (16), with Zr, Al, Ti, Sn, Zn, Mg type alloying elements (film thickness from about 500 to 2,500 Angstroms).
Referring to FIG. 1[0032] b, which in cross-sectional representation illustrates the next process step in the first embodiment of this invention. Shown is the chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a thick layer of pure copper 17. Note, the pure copper film 17 tends to planarize the surface of trench (channel) 13.
Referring to FIG. 1[0033] c, which in cross-sectional representation illustrates the next process step in yet another embodiment of this invention. Shown is a special, annealing step, in inert atmosphere or vacuum, temperature from about 250 to 450° C., to enhance copper alloy formation 18 throughout the film, emanating as a diffusion source from alloy layer 16.
Referring FIG. 2[0034] a, which in cross-sectional representation, sketches the starting point for the second embodiment of this invention. As a background, provided by Prior Art methods are the following: a semiconductor silicon substrate 20 with the first level of metal copper wiring 21 being defined, embedded in the first layer of insulator 22, silicon oxide SiO_x. The invention starts with these conventional layers being provided by Prior Art methods, in addition, to patterned and etched via holes (not shown in Figs.) and trenches (channels) 23 in deposited insulating material 24. A metal “seed layer” and metal diffusion barrier layer beneath the metal copper wiring layers is deposited (too thin, not shown in Figs.). To obtain adequate liner coverage using collimated reactive sputtered, physical vapor deposition (PVD), TaN, Ti/TiN, TiN, WN liners (diffusion barrier) and seed layers, a larger liner thickness must be applied.
Referring again to FIG. 2[0035] a, which in cross-sectional representation illustrates the second embodiment of this invention, which is the chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a thick layer of pure copper 26. Note the thick copper layer 26 tends to planarize the surface. For completeness and showing diligence, the following are the chemical vapor deposition (CVD) conditions used for the present invention: reactant gases (hfac)Cu(tmvs), pressures of about 10 mTorr to 700 Torr, gas flows from about 10 sccm to 2 slm, temperatures about 150 to 250° C., deposition rates from about 50 to 2,000 Angstroms/min. In addition, the following are electrochemical deposition (ECD) conditions used for the present invention: solution of sulfuric acid, temperature of about 25° C., deposition rate of about 1,000 to 10,000 Angstroms/min.
Referring to FIG. 2[0036] b, which in cross-sectional representation illustrates the next process step in the second embodiment of this invention. Shown is the relatively thick physical vapor deposition (PVD) or sputtering of a copper alloy film 27, with Zr, Al, Ti, Sn, Zn, Mg type alloying elements (film thickness from about 500 to 2,500 Angstroms). For completeness and showing diligence, the following are the physical vapor deposition (PVD) or sputtering conditions used for the present invention: target compositions of between 0.5 to 5 atomic percent with alloy compositions of approximately target compositions, Ar sputter gas pressures between 10 mTorr to 100 mTorr, power of from about 100 to 2,000 Watts, DC Magnetron with no reverse bias, DC volts from about 100 to 500 V, substrate temperatures from 100 to 300° C., deposition rates from 50 to 500 Angstroms/min.
Referring to FIG. 2[0037] c, which in cross-sectional representation illustrates the next process step in yet another embodiment of this invention. Shown is a special, annealing step, in inert atmosphere or vacuum, temperature from about 250 to 450° C., to enhance copper alloy formation 28 throughout the film, emanating as a diffusion source from alloy layer 27. For completeness and showing diligence, the following are conditions used for the present invention: all inert ambient or atmospheres of N₂, Ar, H₂, pressures from vacuum to 1 atmosphere, times from 30 sec to 2 hr. at temperatures from 250° to 450° C. Alloy compositions achieved by these two different methods achieve good resistivities of almost that of pure copper (close to single crystal), that is: near ˜2 micro-Ohm-cm (for pure copper) with alloys in the resistivity range of from about 1.8 to 2.2 micro-Ohm-cm.
The final process steps are chemical mechanical polish (CMP) of excess conducting metal, in a manner to form conducting lines and vias without dishing. [0038]
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.[0039]

Claims

What is claimed is:

1. A method of fabricating an integrated circuit on a substrate, the method comprising:

providing a substrate or substrate module;

providing a substrate having a layer of dielectric, interlevel dielectric (ILD), or an interconnect line layer, or device contact region to P-N junctions;

providing a first level of conducting wiring being defined and embedded in a first layer of insulator;

providing patterned and etched via holes and trenches (channels) in deposited insulating material;

depositing (blanket) a thin via hole and trench barrier liner material which is a diffusion barrier;

depositing (alternate Method #1) an alloyed thin seed layer by physical vapor deposition (PVD) followed by chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper;

depositing (alternate Method #2) a thick layer of pure copper by chemical vapor deposition (CVD) or electrochemical deposition (ECD) followed by an alloyed layer by physical vapor deposition (PVD);

annealing by separate low temperature annealing steps (for said Methods #1 and #2 above) to enhance copper alloy formation;

polishing the excess conducting metal back by chemical mechanical polishing (CMP) and repeating the above process steps to make multilevel conducting layers by this integrated method.

2. The method of claim 1, wherein said substrate is semiconductor single crystal silicon or is a ceramic module, with integrated circuits therein.

3. The method of claim 1, wherein the trench or channel and said via hole contact comprises a diffusion barrier liner, which also aids adhesion, liner type materials comprised of TaN, TiN, WN and can be formed by reactive sputtering.

4. The method of claim 1, wherein the thin conformal alloyed seed layer, thickness from about 500 to 2,500 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).

5. The method of claim 1, wherein the chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper planarizes the trench/via surface, thickness range from about 3,000 to 15,000 Angstroms.

6. The method of claim 1, wherein the planar alloyed layer, thickness from about 500 to 5,000 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).

7. The method of claim 1, wherein the annealing by separate low temperature annealing steps, depending on the metal stack structure, to enhance copper metal alloy formation is performed in a low temperature range from about 250 to 450° C.

8. The method of claim 1, wherein the conducting structures are fabricating by repeating the integrated process described herein.

9. The method of claim 1, wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP) or etching.

10. The method of claim 1, wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good fill properties for high aspect ratio vias and trenches, hence improving reliability.

11. The method of claim 1, wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good adhesion properties with insulating films and resist both oxidation/corrosion and electromigration, hence improving reliability.

12. A method of fabricating an integrated circuit on a substrate to form alloyed copper interconnect lines and vias (said alternate Method #1) comprising the following steps:

providing a substrate or substrate module with integrated circuits therein;

depositing (blanket) a thin via hole and trench barrier liner material, e.g., TaN, TiN, WN, which is a diffusion barrier;

depositing an alloyed thin conformal copper seed layer, e.g., Zr, Al, Ti, Sn, Zn, Mg, by physical vapor deposition (PVD), sputtering from an alloyed target;

depositing by chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a thick layer of pure copper, planarizing the surface;

annealing by a special low temperature annealing step to enhance copper alloy formation of metal stack;

polishing the excess conducting metal back by chemical mechanical polishing (CMP) and repeating the above process steps to make multilevel conducting layers, which are corrosion/oxidation and electromigration resistant, by this integrated method.

13. The method of claim 12, wherein said substrate is semiconductor single crystal silicon or is a ceramic module, with integrated circuits therein.

14. The method of claim 12, wherein the trench or channel and said via hole contact comprises a diffusion barrier liner, which also aids adhesion, liner type materials comprised of TaN, TiN, WN and can be formed by reactive sputtering.

15. The method of claim 12, wherein the thin conformal alloyed seed layer, thickness from about 500 to 2,500 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).

16. The method of claim 12, wherein the chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper planarizes the trench/via surface and is in a thickness range from about 3,000 to 15,000 Angstroms.

17. The method of claim 12, wherein the annealing by separate low temperature annealing steps, depending on the metal stack structure, to enhance copper metal alloy formation is performed in a low temperature range from about 250 to 450° C.

18. The method of claim 12, wherein the conducting structures are fabricating by repeating the integrated process described herein.

19. The method of claim 12, wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP) or etching.

20. The method of claim 12, wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good fill properties for high aspect ratio vias and trenches, hence improving reliability.

21. The method of claim 12, wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good adhesion properties with insulating films and resist both oxidation/corrosion and electromigration, hence improving reliability.

22. A method of fabricating an integrated circuit on a substrate to form alloyed copper interconnect lines and vias (said alternate Method #2) comprising the following:

providing a substrate or substrate module with integrated circuits therein;

depositing by chemical vapor deposition (CVD) or electrochemical deposition (ECD) of a thick layer of pure copper, planarizing the surface;

depositing an alloyed planar copper layer, e.g., Zr, Al, Ti, Sn, Zn, Mg, by physical vapor deposition (PVD), sputtering from an alloyed target;

23. The method of claim 22, wherein said substrate is semiconductor single crystal silicon or is a ceramic module, with integrated circuits therein.

24. The method of claim 22, wherein the trench or channel and said via hole contact comprises a diffusion barrier liner, which also aids adhesion, liner type materials comprised of TaN, TiN, WN and can be formed by reactive sputtering.

25. The method of claim 22, wherein the chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a thick layer of pure copper planarizes the trench/via surface and is in a thickness range from about 3,000 to 15,000 Angstroms.

26. The method of claim 22, wherein the planar alloyed layer, thickness from about 500 to 2,500 Angstroms, can be composed of the following copper alloying metals, i.e., Zr, Al, Ti, Sn, Zn, Mg, sputtered from a target which contains the alloyed material, (physical vapor deposition).

27. The method of claim 22, wherein the annealing by separate low temperature annealing steps, depending on the metal stack structure, to enhance copper metal alloy formation is performed in a low temperature range from about 250 to 450° C.

28. The method of claim 22, wherein the conducting structures are fabricating by repeating the integrated process described herein.

29. The method of claim 22, wherein each level of conducting structure is planarized by removing excess conducting material, include planarization by chemical mechanical polish (CMP) or etching.

30. The method of claim 22, wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good fill properties for high aspect ratio vias and trenches, hence improving reliability.

31. The method of claim 22, wherein the unique copper metal alloyed conducting interconnect lines and via structures, produced by this process, have good adhesion properties with insulating films and resist both oxidation/corrosion and electromigration, hence improving reliability.