DE69621116T2 - Selbstprüfende asynchrone datenpuffer - Google Patents

Selbstprüfende asynchrone datenpuffer

Info

Publication number
DE69621116T2
DE69621116T2 DE69621116T DE69621116T DE69621116T2 DE 69621116 T2 DE69621116 T2 DE 69621116T2 DE 69621116 T DE69621116 T DE 69621116T DE 69621116 T DE69621116 T DE 69621116T DE 69621116 T2 DE69621116 T2 DE 69621116T2
Authority
DE
Germany
Prior art keywords
counter
output
buffer
write
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69621116T
Other languages
English (en)
Other versions
DE69621116D1 (de
Inventor
Nils Ernkell
Magnus Sahl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Application granted granted Critical
Publication of DE69621116D1 publication Critical patent/DE69621116D1/de
Publication of DE69621116T2 publication Critical patent/DE69621116T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE69621116T 1995-01-20 1996-01-19 Selbstprüfende asynchrone datenpuffer Expired - Lifetime DE69621116T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/376,147 US5633878A (en) 1995-01-20 1995-01-20 Self-diagnostic data buffers
PCT/SE1996/000053 WO1996022569A1 (en) 1995-01-20 1996-01-19 Self-diagnostic asynchronous data buffers

Publications (2)

Publication Number Publication Date
DE69621116D1 DE69621116D1 (de) 2002-06-13
DE69621116T2 true DE69621116T2 (de) 2002-11-07

Family

ID=23483894

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69621116T Expired - Lifetime DE69621116T2 (de) 1995-01-20 1996-01-19 Selbstprüfende asynchrone datenpuffer

Country Status (7)

Country Link
US (1) US5633878A (de)
EP (1) EP0804762B1 (de)
JP (1) JPH10512693A (de)
AU (1) AU4593096A (de)
CA (1) CA2210153A1 (de)
DE (1) DE69621116T2 (de)
WO (1) WO1996022569A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10124268A (ja) * 1996-08-30 1998-05-15 Canon Inc 印字制御装置
US6266385B1 (en) 1997-12-23 2001-07-24 Wireless Facilities, Inc. Elastic store for wireless communication systems
US5884101A (en) * 1998-04-17 1999-03-16 I-Cube, Inc. Apparatus for detecting data buffer faults
US6928593B1 (en) * 2000-09-18 2005-08-09 Intel Corporation Memory module and memory component built-in self test

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3751649A (en) * 1971-05-17 1973-08-07 Marcrodata Co Memory system exerciser
FR2246023B1 (de) * 1973-09-05 1976-10-01 Honeywell Bull Soc Ind
US4130240A (en) * 1977-08-31 1978-12-19 International Business Machines Corporation Dynamic error location
JPS59185097A (ja) * 1983-04-04 1984-10-20 Oki Electric Ind Co Ltd 自己診断機能付メモリ装置
US4692893A (en) * 1984-12-24 1987-09-08 International Business Machines Corp. Buffer system using parity checking of address counter bit for detection of read/write failures
JPH0713879B2 (ja) * 1985-06-21 1995-02-15 三菱電機株式会社 半導体記憶装置
JP2527935B2 (ja) * 1986-05-19 1996-08-28 株式会社 アドバンテスト 半導体メモリ試験装置
US4831625A (en) * 1986-12-11 1989-05-16 Texas Instruments Incorporated Easily cascadable and testable cache memory
CA1286420C (en) * 1987-10-14 1991-07-16 Youssef Alfred Geadah Fifo buffer controller
FR2642214B1 (fr) * 1988-12-30 1992-11-20 Cit Alcatel Systeme de detection d'ecrasement de donnees dans une memoire tampon, notamment pour un commutateur de donnees
JPH0387000A (ja) * 1989-08-30 1991-04-11 Mitsubishi Electric Corp 半導体記憶装置
DE4244275C1 (de) * 1992-12-28 1994-07-21 Ibm Nachprüfung der Datenintegrität bei gepufferter Datenübertragung
US5469443A (en) * 1993-10-01 1995-11-21 Hal Computer Systems, Inc. Method and apparatus for testing random access memory

Also Published As

Publication number Publication date
AU4593096A (en) 1996-08-07
WO1996022569A1 (en) 1996-07-25
CA2210153A1 (en) 1996-07-25
EP0804762B1 (de) 2002-05-08
EP0804762A1 (de) 1997-11-05
JPH10512693A (ja) 1998-12-02
DE69621116D1 (de) 2002-06-13
US5633878A (en) 1997-05-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition