DE69618747D1 - Halbleiterspeicheranordnung mit niedrigem Leckstrom und verbessertem Datenschutz - Google Patents

Halbleiterspeicheranordnung mit niedrigem Leckstrom und verbessertem Datenschutz

Info

Publication number
DE69618747D1
DE69618747D1 DE69618747T DE69618747T DE69618747D1 DE 69618747 D1 DE69618747 D1 DE 69618747D1 DE 69618747 T DE69618747 T DE 69618747T DE 69618747 T DE69618747 T DE 69618747T DE 69618747 D1 DE69618747 D1 DE 69618747D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
leakage current
data protection
low leakage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69618747T
Other languages
English (en)
Other versions
DE69618747T2 (de
Inventor
Itsuro Iwakiri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69618747D1 publication Critical patent/DE69618747D1/de
Publication of DE69618747T2 publication Critical patent/DE69618747T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
DE69618747T 1995-11-07 1996-10-22 Halbleiterspeicheranordnung mit niedrigem Leckstrom und verbessertem Datenschutz Expired - Lifetime DE69618747T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP28879095 1995-11-07
JP7288790A JPH09134591A (ja) 1995-11-07 1995-11-07 半導体メモリ装置

Publications (2)

Publication Number Publication Date
DE69618747D1 true DE69618747D1 (de) 2002-03-14
DE69618747T2 DE69618747T2 (de) 2004-05-06

Family

ID=17734763

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69618747T Expired - Lifetime DE69618747T2 (de) 1995-11-07 1996-10-22 Halbleiterspeicheranordnung mit niedrigem Leckstrom und verbessertem Datenschutz

Country Status (6)

Country Link
US (1) US5781481A (de)
EP (1) EP0773550B1 (de)
JP (1) JPH09134591A (de)
KR (1) KR100327780B1 (de)
DE (1) DE69618747T2 (de)
TW (1) TW332333B (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254275A (ja) * 1994-01-31 1995-10-03 Toshiba Corp 半導体記憶装置
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5923601A (en) * 1996-09-30 1999-07-13 Advanced Micro Devices, Inc. Memory array sense amplifier test and characterization
US5920517A (en) * 1996-09-30 1999-07-06 Advanced Micro Devices, Inc. Memory array test and characterization using isolated memory cell power supply
US5930185A (en) * 1997-09-26 1999-07-27 Advanced Micro Devices, Inc. Data retention test for static memory cell
US5936892A (en) * 1996-09-30 1999-08-10 Advanced Micro Devices, Inc. Memory cell DC characterization apparatus and method
JP3478953B2 (ja) * 1997-09-03 2003-12-15 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
DE19738642A1 (de) * 1997-09-04 1999-03-11 Clariant Gmbh Farbmittel mit optisch variablen Eigenschaften
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
US6628564B1 (en) * 1998-06-29 2003-09-30 Fujitsu Limited Semiconductor memory device capable of driving non-selected word lines to first and second potentials
KR100284743B1 (ko) * 1999-01-06 2001-03-15 윤종용 저집적 디램 콘트롤러 장치와 연결되는 고집적 디램 반도체 장치
US6373753B1 (en) * 1999-02-13 2002-04-16 Robert J. Proebsting Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
US6356485B1 (en) 1999-02-13 2002-03-12 Integrated Device Technology, Inc. Merging write cycles by comparing at least a portion of the respective write cycle addresses
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
JP2001160296A (ja) 1999-12-01 2001-06-12 Toshiba Corp 電圧レベル変換回路及びこれを用いた半導体記憶装置
JP4651766B2 (ja) * 1999-12-21 2011-03-16 富士通セミコンダクター株式会社 半導体記憶装置
US6343044B1 (en) * 2000-10-04 2002-01-29 International Business Machines Corporation Super low-power generator system for embedded applications
US6510088B2 (en) 2001-03-22 2003-01-21 Winbond Electronics Corporation Semiconductor device having reduced leakage and method of operating the same
JP3520283B2 (ja) * 2002-04-16 2004-04-19 沖電気工業株式会社 半導体記憶装置
KR100526889B1 (ko) * 2004-02-10 2005-11-09 삼성전자주식회사 핀 트랜지스터 구조
US7227383B2 (en) 2004-02-19 2007-06-05 Mosaid Delaware, Inc. Low leakage and data retention circuitry
JP2008065972A (ja) * 2006-08-10 2008-03-21 Nec Electronics Corp 半導体記憶装置
FR2959057B1 (fr) * 2010-04-20 2012-07-20 St Microelectronics Crolles 2 Dispositif de memoire vive dynamique avec circuiterie amelioree de commande des lignes de mots.
US8547777B2 (en) * 2010-12-22 2013-10-01 Intel Corporation Nor logic word line selection
CN102332303B (zh) * 2011-07-13 2014-07-23 清华大学 用于快闪存储器的负电压电平转换电路
JP2013030827A (ja) * 2011-07-26 2013-02-07 Toshiba Corp レベルシフト回路
CN104882162B (zh) * 2015-06-12 2019-05-31 中国电子科技集团公司第四十七研究所 字线电压转换驱动电路
US9882566B1 (en) * 2017-01-10 2018-01-30 Ememory Technology Inc. Driving circuit for non-volatile memory
US10509426B2 (en) 2018-05-02 2019-12-17 Analog Devices Global Unlimited Company Methods and circuits for controlling and/or reducing current leakage during a low-power or inactive mode

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60209996A (ja) * 1984-03-31 1985-10-22 Toshiba Corp 半導体記憶装置
US5257238A (en) * 1991-07-11 1993-10-26 Micron Technology, Inc. Dynamic memory having access transistor turn-off state
EP0559995B1 (de) * 1992-03-11 1998-09-16 STMicroelectronics S.r.l. Dekodierschaltung fähig zur Ubertragung von positiven und negativen Spannungen
US5416747A (en) * 1992-07-15 1995-05-16 Kawasaki Steel Corporation Semiconductor memory driven at low voltage
US5410508A (en) * 1993-05-14 1995-04-25 Micron Semiconductor, Inc. Pumped wordlines
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置

Also Published As

Publication number Publication date
EP0773550A3 (de) 1999-05-19
EP0773550B1 (de) 2002-01-23
DE69618747T2 (de) 2004-05-06
TW332333B (en) 1998-05-21
EP0773550A2 (de) 1997-05-14
US5781481A (en) 1998-07-14
JPH09134591A (ja) 1997-05-20
KR100327780B1 (ko) 2002-08-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: PUSCHMANN & BORCHERT, 82041 OBERHACHING

8327 Change in the person/name/address of the patent owner

Owner name: OKI SEMICONDUCTOR CO.,LTD., TOKYO, JP