DE69421480D1 - Halbleiterspeicheranordnung und Betriebsverfahren dafür - Google Patents

Halbleiterspeicheranordnung und Betriebsverfahren dafür

Info

Publication number
DE69421480D1
DE69421480D1 DE69421480T DE69421480T DE69421480D1 DE 69421480 D1 DE69421480 D1 DE 69421480D1 DE 69421480 T DE69421480 T DE 69421480T DE 69421480 T DE69421480 T DE 69421480T DE 69421480 D1 DE69421480 D1 DE 69421480D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
operating method
method therefor
therefor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69421480T
Other languages
English (en)
Other versions
DE69421480T2 (de
Inventor
Yasuhiro Tanaka
Tetsuya Tanabe
Satoru Tanoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Application granted granted Critical
Publication of DE69421480D1 publication Critical patent/DE69421480D1/de
Publication of DE69421480T2 publication Critical patent/DE69421480T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
DE69421480T 1993-08-31 1994-08-26 Halbleiterspeicheranordnung und Betriebsverfahren dafür Expired - Fee Related DE69421480T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21602893A JP3178946B2 (ja) 1993-08-31 1993-08-31 半導体記憶装置及びその駆動方法

Publications (2)

Publication Number Publication Date
DE69421480D1 true DE69421480D1 (de) 1999-12-09
DE69421480T2 DE69421480T2 (de) 2000-06-15

Family

ID=16682170

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421480T Expired - Fee Related DE69421480T2 (de) 1993-08-31 1994-08-26 Halbleiterspeicheranordnung und Betriebsverfahren dafür

Country Status (5)

Country Link
US (1) US5511030A (de)
EP (1) EP0640976B1 (de)
JP (1) JP3178946B2 (de)
KR (1) KR100263574B1 (de)
DE (1) DE69421480T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5361227A (en) * 1991-12-19 1994-11-01 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
US5587951A (en) * 1995-08-04 1996-12-24 Atmel Corporation High speed, low voltage non-volatile memory
KR100327711B1 (ko) * 1996-09-30 2002-03-08 칼 하인쯔 호르닝어 Ｄｒａｍ
US6094398A (en) * 1996-09-30 2000-07-25 Siemens Aktiengesellschaft DRAM including an address space divided into individual blocks having memory cells activated by row address signals
KR100269597B1 (ko) * 1997-05-29 2000-10-16 김영환 반도체 메모리
US7218564B2 (en) * 2004-07-16 2007-05-15 Promos Technologies Inc. Dual equalization devices for long data line pairs
CN103187087B (zh) * 2013-03-19 2016-03-23 西安华芯半导体有限公司 存储器
US10090027B2 (en) * 2016-05-25 2018-10-02 Ememory Technology Inc. Memory system with low read power
WO2019162802A1 (ja) * 2018-02-23 2019-08-29 株式会社半導体エネルギー研究所 記憶装置およびその動作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60253093A (ja) * 1984-05-30 1985-12-13 Fujitsu Ltd 半導体記憶装置
JPS6363196A (ja) * 1986-09-02 1988-03-19 Fujitsu Ltd 半導体記憶装置
JPS63166090A (ja) * 1986-12-26 1988-07-09 Toshiba Corp スタティック型メモリ
JPH01171195A (ja) * 1987-12-25 1989-07-06 Sony Corp メモリ装置
KR940008296B1 (ko) * 1991-06-19 1994-09-10 삼성전자 주식회사 고속 센싱동작을 수행하는 센스앰프
JPH0516117A (ja) * 1991-07-16 1993-01-26 Kubota Corp 無機質押出建材の凹凸模様付け方法

Also Published As

Publication number Publication date
JP3178946B2 (ja) 2001-06-25
DE69421480T2 (de) 2000-06-15
KR950006854A (ko) 1995-03-21
EP0640976A2 (de) 1995-03-01
KR100263574B1 (ko) 2000-08-01
EP0640976B1 (de) 1999-11-03
US5511030A (en) 1996-04-23
EP0640976A3 (de) 1995-10-11
JPH0773663A (ja) 1995-03-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee