DE69714379T2 - Integrierte Halbleiterspeicheranordnung und Kommunikationsverfahren dafür - Google Patents

Integrierte Halbleiterspeicheranordnung und Kommunikationsverfahren dafür

Info

Publication number
DE69714379T2
DE69714379T2 DE69714379T DE69714379T DE69714379T2 DE 69714379 T2 DE69714379 T2 DE 69714379T2 DE 69714379 T DE69714379 T DE 69714379T DE 69714379 T DE69714379 T DE 69714379T DE 69714379 T2 DE69714379 T2 DE 69714379T2
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
communication method
method therefor
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69714379T
Other languages
English (en)
Other versions
DE69714379D1 (de
Inventor
Robert Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
STMicroelectronics Ltd Great Britain
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Ltd Great Britain, SGS Thomson Microelectronics Ltd filed Critical STMicroelectronics Ltd Great Britain
Application granted granted Critical
Publication of DE69714379D1 publication Critical patent/DE69714379D1/de
Publication of DE69714379T2 publication Critical patent/DE69714379T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
DE69714379T 1996-10-31 1997-10-20 Integrierte Halbleiterspeicheranordnung und Kommunikationsverfahren dafür Expired - Fee Related DE69714379T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9622685.7A GB9622685D0 (en) 1996-10-31 1996-10-31 An integrated circuit device and method of communication therewith

Publications (2)

Publication Number Publication Date
DE69714379D1 DE69714379D1 (de) 2002-09-05
DE69714379T2 true DE69714379T2 (de) 2003-03-20

Family

ID=10802228

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69714379T Expired - Fee Related DE69714379T2 (de) 1996-10-31 1997-10-20 Integrierte Halbleiterspeicheranordnung und Kommunikationsverfahren dafür

Country Status (5)

Country Link
US (1) US6041378A (de)
EP (1) EP0840218B1 (de)
JP (1) JP3929572B2 (de)
DE (1) DE69714379T2 (de)
GB (1) GB9622685D0 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9622683D0 (en) * 1996-10-31 1997-01-08 Sgs Thomson Microelectronics Message protocol
GB9810512D0 (en) 1998-05-15 1998-07-15 Sgs Thomson Microelectronics Detecting communication errors across a chip boundary
US6567932B2 (en) * 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6601189B1 (en) * 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6792562B1 (en) * 2000-03-06 2004-09-14 Pc-Doctor, Inc. Format for extensible error and event codes
DE10056198A1 (de) * 2000-11-13 2002-02-14 Infineon Technologies Ag Kommunikationssystem zum Austausch von Daten unter Verwendung eines zusätzlichen Prozessors
US7168032B2 (en) * 2000-12-15 2007-01-23 Intel Corporation Data synchronization for a test access port
DE60125360D1 (de) 2001-09-18 2007-02-01 Sgs Thomson Microelectronics Abfrageprüfgerät, das Überabtastung zur Synchronisierung verwendet
WO2003101047A2 (en) * 2002-05-24 2003-12-04 Baker Hughes Incorporated A method and apparatus for high speed communication with a downhole tool
US7702964B2 (en) * 2004-05-11 2010-04-20 Qualcomm Incorporated Compression of data traces for an integrated circuit with multiple memories
US7451367B2 (en) * 2006-02-14 2008-11-11 Atmel Corporation Accessing sequential data in microcontrollers
US7610528B2 (en) * 2006-02-14 2009-10-27 Atmel Corporation Configuring flash memory
GB2445166A (en) * 2006-12-27 2008-07-02 Advanced Risc Mach Ltd Integrated circuit with an interface that can selectively communicate a diagnostic signal or a functional signal to external devices.
CN112988653B (zh) * 2019-12-16 2024-04-12 广州希姆半导体科技有限公司 数据处理电路、装置以及方法
CN112463662B (zh) * 2020-12-16 2024-04-05 福州创实讯联信息技术有限公司 一种用户态控制i2c设备的方法与终端

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0165600B1 (de) * 1984-06-20 1991-11-21 Convex Computer Corporation Ein-/Ausgabebus für Rechner
US4935867A (en) * 1986-03-04 1990-06-19 Advanced Micro Devices, Inc. Signal processor memory management unit with indirect addressing using selectable offsets and modulo values for indexed address calculations
US5452432A (en) * 1990-08-14 1995-09-19 Chips And Technologies, Inc. Partially resettable, segmented DMA counter
DE69415600T2 (de) * 1993-07-28 1999-07-15 Koninkl Philips Electronics Nv Mikrokontroller mit hardwaremässiger Fehlerbeseitigungsunterstützung nach dem Boundary-Scanverfahren
EP0652516A1 (de) * 1993-11-03 1995-05-10 Advanced Micro Devices, Inc. Integrierter Mikroprozessor
US5596734A (en) * 1993-12-17 1997-01-21 Intel Corporation Method and apparatus for programming embedded memories of a variety of integrated circuits using the IEEE test access port
US5828825A (en) * 1993-12-22 1998-10-27 Intel Corporation Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port
US5630048A (en) * 1994-05-19 1997-05-13 La Joie; Leslie T. Diagnostic system for run-time monitoring of computer operations
JP2752592B2 (ja) * 1994-12-28 1998-05-18 日本ヒューレット・パッカード株式会社 マイクロプロセッサ、マイクロプロセッサ−デバッグツール間信号伝送方法及びトレース方法

Also Published As

Publication number Publication date
EP0840218A1 (de) 1998-05-06
US6041378A (en) 2000-03-21
GB9622685D0 (en) 1997-01-08
JP3929572B2 (ja) 2007-06-13
JPH10198576A (ja) 1998-07-31
DE69714379D1 (de) 2002-09-05
EP0840218B1 (de) 2002-07-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee