DE69421108T2 - Halbleiterspeicheranordnung und Speicher-Initialisierungsverfahren - Google Patents

Halbleiterspeicheranordnung und Speicher-Initialisierungsverfahren

Info

Publication number
DE69421108T2
DE69421108T2 DE69421108T DE69421108T DE69421108T2 DE 69421108 T2 DE69421108 T2 DE 69421108T2 DE 69421108 T DE69421108 T DE 69421108T DE 69421108 T DE69421108 T DE 69421108T DE 69421108 T2 DE69421108 T2 DE 69421108T2
Authority
DE
Germany
Prior art keywords
initialization method
memory device
semiconductor memory
memory
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69421108T
Other languages
English (en)
Other versions
DE69421108D1 (de
Inventor
Kiyotaka Okuzawa Kiyot Okuzawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE69421108D1 publication Critical patent/DE69421108D1/de
Application granted granted Critical
Publication of DE69421108T2 publication Critical patent/DE69421108T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
DE69421108T 1993-01-22 1994-01-21 Halbleiterspeicheranordnung und Speicher-Initialisierungsverfahren Expired - Fee Related DE69421108T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02733593A JP3358030B2 (ja) 1993-01-22 1993-01-22 半導体メモリ装置及びその初期化方法

Publications (2)

Publication Number Publication Date
DE69421108D1 DE69421108D1 (de) 1999-11-18
DE69421108T2 true DE69421108T2 (de) 2000-05-25

Family

ID=12218198

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69421108T Expired - Fee Related DE69421108T2 (de) 1993-01-22 1994-01-21 Halbleiterspeicheranordnung und Speicher-Initialisierungsverfahren

Country Status (4)

Country Link
US (1) US5517451A (de)
EP (1) EP0617428B1 (de)
JP (1) JP3358030B2 (de)
DE (1) DE69421108T2 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5951702A (en) * 1997-04-04 1999-09-14 S3 Incorporated RAM-like test structure superimposed over rows of macrocells with added differential pass transistors in a CPU
US5914901A (en) * 1997-05-30 1999-06-22 Sgs-Thomson Microelectronics S.R.L. Integrated circuit for generating initialization signals for memory cell sensing circuits
US6292416B1 (en) 1998-02-11 2001-09-18 Alliance Semiconductor Corporation Apparatus and method of reducing the pre-charge time of bit lines in a random access memory
KR100386114B1 (ko) * 2001-02-16 2003-06-02 삼성전자주식회사 멀티-입/출력카드를 갖춘 네트워크시스템의 초기화제어장치
JP4338010B2 (ja) * 2002-04-22 2009-09-30 株式会社日立製作所 半導体集積回路装置
US6940771B2 (en) * 2003-01-30 2005-09-06 Sun Microsystems, Inc. Methods and circuits for balancing bitline precharge
KR100761381B1 (ko) * 2006-09-06 2007-09-27 주식회사 하이닉스반도체 비트라인 센스앰프 미스매치판단이 가능한 메모리장치.
KR101155451B1 (ko) 2011-08-31 2012-06-15 테세라, 인코포레이티드 Ｄｒａｍ 보안 소거
US9805802B2 (en) 2015-09-14 2017-10-31 Samsung Electronics Co., Ltd. Memory device, memory module, and memory system
US11600316B2 (en) * 2020-05-28 2023-03-07 Rambus Inc. DRAM security erase
US11557335B2 (en) 2020-07-07 2023-01-17 International Business Machines Corporation Erasing a partition of an SRAM array with hardware support
US11302378B2 (en) * 2020-07-07 2022-04-12 International Business Machines Corporation Semiconductor circuit including an initialization circuit for initializing memory cells and clearing of relatively large blocks of memory
US11862237B2 (en) 2021-07-08 2024-01-02 Changxin Memory Technologies, Inc. Memory and method for writing memory
CN115602208A (zh) * 2021-07-08 2023-01-13 长鑫存储技术有限公司（Cn） 一种存储器及其写入方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
JP2588936B2 (ja) * 1988-07-04 1997-03-12 沖電気工業株式会社 半導体記憶装置
JPH0283892A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
JPH07118196B2 (ja) * 1988-12-28 1995-12-18 株式会社東芝 スタティック型半導体メモリ
US4996671A (en) * 1989-02-18 1991-02-26 Sony Corporation Semiconductor memory device
KR940008717B1 (ko) * 1989-03-06 1994-09-26 마쯔시다덴기산교 가부시기가이샤 다이내믹 ram의 판독회로
US5245579A (en) * 1989-11-24 1993-09-14 Sharp Kabushiki Kaisha Semiconductor memory device
JP2963504B2 (ja) * 1990-07-23 1999-10-18 沖電気工業株式会社 半導体記憶装置
DE69121503T2 (de) * 1990-09-29 1997-02-13 Nec Corp Halbleiterspeicheranordnung mit einer rauscharmen Abfühlstruktur
JP2630059B2 (ja) * 1990-11-09 1997-07-16 日本電気株式会社 半導体メモリ装置
KR940007000B1 (ko) * 1991-05-24 1994-08-03 삼성전자 주식회사 개선된 라이트 동작을 가지는 반도체 메모리 장치
GB2259589A (en) * 1991-09-12 1993-03-17 Motorola Inc Self - timed random access memories
US5301157A (en) * 1992-06-01 1994-04-05 Micron Technology, Inc. Coupling circuit and method for discharging a non-selected bit line during accessing of a memory storage cell
JPH05342873A (ja) * 1992-06-10 1993-12-24 Nec Corp 半導体記憶装置

Also Published As

Publication number Publication date
JPH06223561A (ja) 1994-08-12
EP0617428A1 (de) 1994-09-28
EP0617428B1 (de) 1999-10-13
US5517451A (en) 1996-05-14
DE69421108D1 (de) 1999-11-18
JP3358030B2 (ja) 2002-12-16

Similar Documents

Publication Publication Date Title
DE69419469D1 (de) Halbleiterbauelement und Halbleiterspeichervorrichtung
DE69518343T2 (de) Halbleiterspeicheranordnung
DE69603632D1 (de) Halbleiter-Speicheranordnung
DE69521159D1 (de) Halbleiterspeicheranordnung
DE69422901T2 (de) Halbleiterspeicheranordnung
DE69413602D1 (de) Halbleiteranordnung und Herstellungsverfahren
DE69424728D1 (de) Halbleiteranordnung und zugehörige Herstellungsmethode
DE4407210B4 (de) Halbleiterspeicherbauelementaufbau
DE69615783D1 (de) Halbleiterspeicheranordnung
DE69512700D1 (de) Halbleiterspeicheranordnung
DE69432846D1 (de) Halbleiterspeichereinrichtung
DE69427443D1 (de) Halbleiterspeicheranordnung
KR960012496A (ko) 반도체기억장치 및 그 제조방법
KR960012510A (ko) 반도체 메모리 장치
DE69606170T2 (de) Halbleiterspeicheranordnung
DE69421108T2 (de) Halbleiterspeicheranordnung und Speicher-Initialisierungsverfahren
KR970004011A (ko) 반도체기억장치 및 그 제조방법
DE69427107T2 (de) Halbleiterspeicheranordnung
DE69421480T2 (de) Halbleiterspeicheranordnung und Betriebsverfahren dafür
DE69521066D1 (de) Halbleiterspeicheranordnung
DE69321544D1 (de) Halbleiterspeicheranordnung
DE69423996T2 (de) Halbleiterspeicheranordnung
KR960011705A (ko) 반도체 메모리 장치
DE69420195T2 (de) Halbleiterspeicheranordnung
FI961853A (fi) Puolijohdemuistilaite

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee