DE69619751D1 - Halbleiterspeicheranordnung mit seriellem Zugrifftor - Google Patents
Halbleiterspeicheranordnung mit seriellem ZugrifftorInfo
- Publication number
- DE69619751D1 DE69619751D1 DE69619751T DE69619751T DE69619751D1 DE 69619751 D1 DE69619751 D1 DE 69619751D1 DE 69619751 T DE69619751 T DE 69619751T DE 69619751 T DE69619751 T DE 69619751T DE 69619751 D1 DE69619751 D1 DE 69619751D1
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- serial access
- access gate
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7238019A JP2783214B2 (ja) | 1995-09-18 | 1995-09-18 | 半導体メモリ装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69619751D1 true DE69619751D1 (de) | 2002-04-18 |
DE69619751T2 DE69619751T2 (de) | 2002-10-02 |
Family
ID=17023958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69619751T Expired - Lifetime DE69619751T2 (de) | 1995-09-18 | 1996-08-02 | Halbleiterspeicheranordnung mit seriellem Zugrifftor |
Country Status (5)
Country | Link |
---|---|
US (1) | US5757701A (de) |
EP (1) | EP0763827B1 (de) |
JP (1) | JP2783214B2 (de) |
KR (1) | KR100242482B1 (de) |
DE (1) | DE69619751T2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6292427B1 (en) * | 2000-10-12 | 2001-09-18 | Virage Logic Corp. | Hierarchical sense amp and write driver circuitry for compilable memory |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE68923573T2 (de) * | 1988-03-31 | 1996-01-18 | Sony Corp | Eingangsschaltungen. |
JP2633645B2 (ja) * | 1988-09-13 | 1997-07-23 | 株式会社東芝 | 半導体メモリ装置 |
DE69122293T2 (de) * | 1990-04-27 | 1997-04-24 | Nec Corp | Halbleiterspeicheranordnung |
JPH0562461A (ja) * | 1991-04-09 | 1993-03-12 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP3105319B2 (ja) * | 1991-12-19 | 2000-10-30 | 株式会社 沖マイクロデザイン | シリアルアクセスメモリ |
-
1995
- 1995-09-18 JP JP7238019A patent/JP2783214B2/ja not_active Expired - Fee Related
-
1996
- 1996-07-30 KR KR1019960031369A patent/KR100242482B1/ko not_active IP Right Cessation
- 1996-08-02 EP EP96112512A patent/EP0763827B1/de not_active Expired - Lifetime
- 1996-08-02 DE DE69619751T patent/DE69619751T2/de not_active Expired - Lifetime
- 1996-08-05 US US08/691,013 patent/US5757701A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0763827A3 (de) | 1997-12-10 |
DE69619751T2 (de) | 2002-10-02 |
JPH0982087A (ja) | 1997-03-28 |
KR100242482B1 (ko) | 2000-02-01 |
EP0763827B1 (de) | 2002-03-13 |
EP0763827A2 (de) | 1997-03-19 |
JP2783214B2 (ja) | 1998-08-06 |
US5757701A (en) | 1998-05-26 |
KR970017652A (ko) | 1997-04-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC CORP., TOKIO/TOKYO, JP Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: ELPIDA MEMORY, INC., TOKYO, JP |