DE69602013D1 - Parallelverarbeitungsredundanzs-vorrichtung und -verfahren für schnellere zugriffszeit und kleinere matrizeoberfläche - Google Patents

Parallelverarbeitungsredundanzs-vorrichtung und -verfahren für schnellere zugriffszeit und kleinere matrizeoberfläche

Info

Publication number
DE69602013D1
DE69602013D1 DE69602013T DE69602013T DE69602013D1 DE 69602013 D1 DE69602013 D1 DE 69602013D1 DE 69602013 T DE69602013 T DE 69602013T DE 69602013 T DE69602013 T DE 69602013T DE 69602013 D1 DE69602013 D1 DE 69602013D1
Authority
DE
Germany
Prior art keywords
parallel processing
matrice
smaller
access time
faster access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69602013T
Other languages
English (en)
Other versions
DE69602013T2 (de
Inventor
Frankie Roohparvar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of DE69602013D1 publication Critical patent/DE69602013D1/de
Publication of DE69602013T2 publication Critical patent/DE69602013T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
DE69602013T 1995-02-10 1996-02-09 Parallelverarbeitungsredundanzs-vorrichtung und -verfahren für schnellere zugriffszeit und kleinere matrizeoberfläche Expired - Lifetime DE69602013T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/387,018 US5627786A (en) 1995-02-10 1995-02-10 Parallel processing redundancy scheme for faster access times and lower die area
PCT/US1996/001831 WO1996024897A2 (en) 1995-02-10 1996-02-09 Parallel processing redundancy scheme for faster access times and lower die area

Publications (2)

Publication Number Publication Date
DE69602013D1 true DE69602013D1 (de) 1999-05-12
DE69602013T2 DE69602013T2 (de) 1999-08-05

Family

ID=23528088

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69602013T Expired - Lifetime DE69602013T2 (de) 1995-02-10 1996-02-09 Parallelverarbeitungsredundanzs-vorrichtung und -verfahren für schnellere zugriffszeit und kleinere matrizeoberfläche

Country Status (5)

Country Link
US (2) US5627786A (de)
EP (1) EP0808486B1 (de)
AT (1) ATE178724T1 (de)
DE (1) DE69602013T2 (de)
WO (1) WO1996024897A2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081870A (en) * 1997-11-06 2000-06-27 Micron Technology, Inc. Method and apparatus to achieve fast suspend in flash memories
US6077211A (en) * 1998-02-27 2000-06-20 Micron Technology, Inc. Circuits and methods for selectively coupling redundant elements into an integrated circuit
JP3871469B2 (ja) 1998-11-27 2007-01-24 松下電器産業株式会社 半導体メモリ装置および信号線切替回路
US6246615B1 (en) 1998-12-23 2001-06-12 Micron Technology, Inc. Redundancy mapping in a multichip semiconductor package
TWI225863B (en) * 1999-03-24 2005-01-01 Takeda Chemical Industries Ltd Thienopyrimidine compounds, their production and use
JP2001084791A (ja) * 1999-07-12 2001-03-30 Mitsubishi Electric Corp 半導体記憶装置
US6484271B1 (en) 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6728161B1 (en) * 2000-06-30 2004-04-27 Micron Technology, Inc. Zero latency-zero bus turnaround synchronous flash memory
US6851026B1 (en) 2000-07-28 2005-02-01 Micron Technology, Inc. Synchronous flash memory with concurrent write and read operation
US6615307B1 (en) * 2000-05-10 2003-09-02 Micron Technology, Inc. Flash with consistent latency for read operations
US6883044B1 (en) * 2000-07-28 2005-04-19 Micron Technology, Inc. Synchronous flash memory with simultaneous access to one or more banks
US6496425B1 (en) 2000-08-21 2002-12-17 Micron Technology, Inc Multiple bit line column redundancy
US6445625B1 (en) 2000-08-25 2002-09-03 Micron Technology, Inc. Memory device redundancy selection having test inputs
US6504768B1 (en) 2000-08-25 2003-01-07 Micron Technology, Inc. Redundancy selection in memory devices with concurrent read and write
US7978219B1 (en) 2000-08-30 2011-07-12 Kevin Reid Imes Device, network, server, and methods for providing digital images and associated processing information
US8326352B1 (en) 2000-09-06 2012-12-04 Kevin Reid Imes Device, network, server, and methods for providing service requests for wireless communication devices
ITRM20010104A1 (it) * 2001-02-27 2002-08-27 Micron Technology Inc Modo di lettura a compressione di dati per il collaudo di memorie.
JP2004063023A (ja) * 2002-07-30 2004-02-26 Renesas Technology Corp 半導体記憶装置
JP3984209B2 (ja) * 2003-07-31 2007-10-03 株式会社東芝 半導体記憶装置
DE202004012766U1 (de) * 2004-08-14 2006-01-19 Flür, Peter, Dr. System zur Automatisierung von administrativen Routineaufgaben
ITRM20040418A1 (it) * 2004-08-25 2004-11-25 Micron Technology Inc Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie.
KR100645044B1 (ko) * 2004-09-17 2006-11-10 삼성전자주식회사 높은 신뢰도를 갖는 불 휘발성 메모리 장치의 프로그램 방법
US7035152B1 (en) * 2004-10-14 2006-04-25 Micron Technology, Inc. System and method for redundancy memory decoding
US7259373B2 (en) * 2005-07-08 2007-08-21 Nexgensemi Holdings Corporation Apparatus and method for controlled particle beam manufacturing
US7224605B1 (en) * 2006-03-24 2007-05-29 Sandisk Corporation Non-volatile memory with redundancy data buffered in data latches for defective locations
US7324389B2 (en) * 2006-03-24 2008-01-29 Sandisk Corporation Non-volatile memory with redundancy data buffered in remote buffer circuits
US7352635B2 (en) * 2006-03-24 2008-04-01 Sandisk Corporation Method for remote redundancy for non-volatile memory
US7394690B2 (en) * 2006-03-24 2008-07-01 Sandisk Corporation Method for column redundancy using data latches in solid-state memories

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Publication number Priority date Publication date Assignee Title
US4250570B1 (en) * 1976-07-15 1996-01-02 Intel Corp Redundant memory circuit
US4389715A (en) * 1980-10-06 1983-06-21 Inmos Corporation Redundancy scheme for a dynamic RAM
US4459685A (en) * 1982-03-03 1984-07-10 Inmos Corporation Redundancy system for high speed, wide-word semiconductor memories
FR2611301B1 (fr) * 1987-02-24 1989-04-21 Thomson Semiconducteurs Memoire integree avec redondance de colonnes de donnees
JPH01109599A (ja) * 1987-10-22 1989-04-26 Nec Corp 書込み・消去可能な半導体記憶装置
US4807191A (en) * 1988-01-04 1989-02-21 Motorola, Inc. Redundancy for a block-architecture memory
US4885720A (en) * 1988-04-01 1989-12-05 International Business Machines Corporation Memory device and method implementing wordline redundancy without an access time penalty
GB8926004D0 (en) * 1989-11-17 1990-01-10 Inmos Ltd Repairable memory circuit
JPH06111596A (ja) * 1990-10-09 1994-04-22 Texas Instr Inc <Ti> メモリ
JP2596208B2 (ja) * 1990-10-19 1997-04-02 日本電気株式会社 メモリ装置
US5265054A (en) * 1990-12-14 1993-11-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with precharged redundancy multiplexing
JPH05166396A (ja) * 1991-12-12 1993-07-02 Mitsubishi Electric Corp 半導体メモリ装置
US5262994A (en) * 1992-01-31 1993-11-16 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with a multiplexer for selecting an output for a redundant memory access
US5268866A (en) * 1992-03-02 1993-12-07 Motorola, Inc. Memory with column redundancy and localized column redundancy control signals

Also Published As

Publication number Publication date
DE69602013T2 (de) 1999-08-05
WO1996024897A2 (en) 1996-08-15
WO1996024897A3 (en) 1996-10-17
US5808946A (en) 1998-09-15
US5627786A (en) 1997-05-06
EP0808486B1 (de) 1999-04-07
ATE178724T1 (de) 1999-04-15
EP0808486A2 (de) 1997-11-26

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