DE69535672D1 - Synchrone NAND DRAM Architektur - Google Patents
Synchrone NAND DRAM ArchitekturInfo
- Publication number
- DE69535672D1 DE69535672D1 DE69535672T DE69535672T DE69535672D1 DE 69535672 D1 DE69535672 D1 DE 69535672D1 DE 69535672 T DE69535672 T DE 69535672T DE 69535672 T DE69535672 T DE 69535672T DE 69535672 D1 DE69535672 D1 DE 69535672D1
- Authority
- DE
- Germany
- Prior art keywords
- bank
- memory
- array
- high speed
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C11/4045—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell using a plurality of serially connected access transistors, each having a storage capacitor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Databases & Information Systems (AREA)
- Dram (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US348552 | 1994-12-01 | ||
US08/348,552 US5513148A (en) | 1994-12-01 | 1994-12-01 | Synchronous NAND DRAM architecture |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69535672D1 true DE69535672D1 (de) | 2008-01-31 |
DE69535672T2 DE69535672T2 (de) | 2008-12-04 |
Family
ID=23368520
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69526431T Expired - Lifetime DE69526431T2 (de) | 1994-12-01 | 1995-11-30 | Eine synchrone nand-dram-speicherarchitektur |
DE69535672T Expired - Lifetime DE69535672T2 (de) | 1994-12-01 | 1995-11-30 | Synchrone NAND DRAM Architektur |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69526431T Expired - Lifetime DE69526431T2 (de) | 1994-12-01 | 1995-11-30 | Eine synchrone nand-dram-speicherarchitektur |
Country Status (8)
Country | Link |
---|---|
US (2) | US5513148A (de) |
EP (2) | EP0744073B1 (de) |
JP (1) | JPH09507948A (de) |
KR (1) | KR100206063B1 (de) |
AT (1) | ATE216529T1 (de) |
AU (1) | AU4290296A (de) |
DE (2) | DE69526431T2 (de) |
WO (1) | WO1996017355A1 (de) |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5526320A (en) * | 1994-12-23 | 1996-06-11 | Micron Technology Inc. | Burst EDO memory device |
US5668773A (en) * | 1994-12-23 | 1997-09-16 | Micron Technology, Inc. | Synchronous burst extended data out DRAM |
US6525971B2 (en) | 1995-06-30 | 2003-02-25 | Micron Technology, Inc. | Distributed write data drivers for burst access memories |
US5675549A (en) * | 1994-12-23 | 1997-10-07 | Micron Technology, Inc. | Burst EDO memory device address counter |
US5610864A (en) | 1994-12-23 | 1997-03-11 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
US6804760B2 (en) | 1994-12-23 | 2004-10-12 | Micron Technology, Inc. | Method for determining a type of memory present in a system |
US5682354A (en) * | 1995-11-06 | 1997-10-28 | Micron Technology, Inc. | CAS recognition in burst extended data out DRAM |
US5640364A (en) * | 1994-12-23 | 1997-06-17 | Micron Technology, Inc. | Self-enabling pulse trapping circuit |
US5630096A (en) * | 1995-05-10 | 1997-05-13 | Microunity Systems Engineering, Inc. | Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order |
US5729504A (en) * | 1995-12-14 | 1998-03-17 | Micron Technology, Inc. | Continuous burst edo memory device |
US7681005B1 (en) * | 1996-01-11 | 2010-03-16 | Micron Technology, Inc. | Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation |
US6243768B1 (en) | 1996-02-09 | 2001-06-05 | Intel Corporation | Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus |
US5926828A (en) * | 1996-02-09 | 1999-07-20 | Intel Corporation | Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus |
US6009038A (en) * | 1996-05-31 | 1999-12-28 | United Microelectronics Corporation | Addressing unit |
JPH09320269A (ja) * | 1996-05-31 | 1997-12-12 | Nippon Steel Corp | アドレス装置 |
JPH1011966A (ja) * | 1996-06-27 | 1998-01-16 | Mitsubishi Electric Corp | 同期型半導体記憶装置および同期型メモリモジュール |
US6981126B1 (en) * | 1996-07-03 | 2005-12-27 | Micron Technology, Inc. | Continuous interleave burst access |
US6401186B1 (en) | 1996-07-03 | 2002-06-04 | Micron Technology, Inc. | Continuous burst memory which anticipates a next requested start address |
US5784705A (en) * | 1996-07-15 | 1998-07-21 | Mosys, Incorporated | Method and structure for performing pipeline burst accesses in a semiconductor memory |
US5909225A (en) * | 1997-05-30 | 1999-06-01 | Hewlett-Packard Co. | Frame buffer cache for graphics applications |
US5937204A (en) * | 1997-05-30 | 1999-08-10 | Helwett-Packard, Co. | Dual-pipeline architecture for enhancing the performance of graphics memory |
US6002412A (en) * | 1997-05-30 | 1999-12-14 | Hewlett-Packard Co. | Increased performance of graphics memory using page sorting fifos |
KR100295641B1 (ko) * | 1998-01-23 | 2001-08-07 | 김영환 | 글로벌워드라인드라이버 |
US6205482B1 (en) | 1998-02-19 | 2001-03-20 | Ameritech Corporation | System and method for executing a request from a client application |
US6199145B1 (en) * | 1998-02-27 | 2001-03-06 | Intel Corporation | Configurable page closing method and apparatus for multi-port host bridges |
KR100278658B1 (ko) * | 1998-08-27 | 2001-01-15 | 윤종용 | 아날로그 펌핑 구조를 가지는 내부 클락 발생회로 |
TW459229B (en) | 1999-02-24 | 2001-10-11 | Matsushita Electric Ind Co Ltd | Semiconductor memory device |
US6609174B1 (en) * | 1999-10-19 | 2003-08-19 | Motorola, Inc. | Embedded MRAMs including dual read ports |
US6292387B1 (en) | 2000-01-20 | 2001-09-18 | Micron Technology, Inc. | Selective device coupling |
US6392935B1 (en) | 2000-04-03 | 2002-05-21 | Maxtor Corporation | Maximum bandwidth/minimum latency SDRAM interface |
KR100401508B1 (ko) * | 2001-05-25 | 2003-10-17 | 주식회사 하이닉스반도체 | 램버스 디램의 뱅크 제어회로 |
US6779074B2 (en) * | 2001-07-13 | 2004-08-17 | Micron Technology, Inc. | Memory device having different burst order addressing for read and write operations |
US6590817B2 (en) | 2001-07-23 | 2003-07-08 | Micron Technology, Inc. | 6F2 DRAM array with apparatus for stress testing an isolation gate and method |
US7051264B2 (en) * | 2001-11-14 | 2006-05-23 | Monolithic System Technology, Inc. | Error correcting memory and method of operating same |
US7003644B2 (en) * | 2002-03-28 | 2006-02-21 | Seagate Technology Llc | Execution time dependent command schedule optimization |
US7457156B2 (en) * | 2004-09-02 | 2008-11-25 | Micron Technology, Inc. | NAND flash depletion cell structure |
US7392456B2 (en) * | 2004-11-23 | 2008-06-24 | Mosys, Inc. | Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
US7539062B2 (en) | 2006-12-20 | 2009-05-26 | Micron Technology, Inc. | Interleaved memory program and verify method, device and system |
US8070965B2 (en) * | 2007-04-18 | 2011-12-06 | Tarves Robert J Jun | Dual walled dynamic phase separator |
CN102736860B (zh) * | 2011-04-08 | 2015-03-11 | 安凯(广州)微电子技术有限公司 | 同步nand的数据操作系统及方法 |
CN110097917B (zh) * | 2018-01-30 | 2021-03-30 | 长鑫存储技术有限公司 | 存储单元的电容测试装置、方法及半导体存储器 |
US10985162B2 (en) | 2018-12-14 | 2021-04-20 | John Bennett | System for accurate multiple level gain cells |
JP2023532955A (ja) * | 2020-07-09 | 2023-08-01 | マイクロチップ テクノロジー インコーポレイテッド | 時間同期されたハードウェアコントローラ並びに関連するオーディオシステム及び回路 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4602354A (en) * | 1983-01-10 | 1986-07-22 | Ncr Corporation | X-and-OR memory array |
DE3543911A1 (de) * | 1984-12-14 | 1986-06-26 | Mitsubishi Denki K.K., Tokio/Tokyo | Digitale verzoegerungseinheit |
KR940008295B1 (ko) * | 1989-08-28 | 1994-09-10 | 가부시기가이샤 히다찌세이사꾸쇼 | 반도체메모리 |
KR100214435B1 (ko) * | 1990-07-25 | 1999-08-02 | 사와무라 시코 | 동기식 버스트 엑세스 메모리 |
EP0473421B1 (de) * | 1990-08-30 | 1997-10-29 | Nec Corporation | Halbleiterspeicheranordnung |
JP2721931B2 (ja) * | 1990-09-28 | 1998-03-04 | 三菱電機株式会社 | 半導体メモリのためのシリアル選択回路 |
TW198135B (de) * | 1990-11-20 | 1993-01-11 | Oki Electric Ind Co Ltd | |
JP3100622B2 (ja) * | 1990-11-20 | 2000-10-16 | 沖電気工業株式会社 | 同期型ダイナミックram |
JP2564046B2 (ja) * | 1991-02-13 | 1996-12-18 | 株式会社東芝 | 半導体記憶装置 |
US5305263A (en) * | 1991-06-12 | 1994-04-19 | Micron Technology, Inc. | Simplified low power flash write operation |
US5276642A (en) * | 1991-07-15 | 1994-01-04 | Micron Technology, Inc. | Method for performing a split read/write operation in a dynamic random access memory |
US5307314A (en) * | 1991-07-15 | 1994-04-26 | Micron Technology, Inc. | Split read/write dynamic random access memory |
US5357462A (en) * | 1991-09-24 | 1994-10-18 | Kabushiki Kaisha Toshiba | Electrically erasable and programmable non-volatile semiconductor memory with automatic write-verify controller |
DE69225044T2 (de) * | 1991-11-18 | 1998-10-22 | Toshiba Kawasaki Kk | Dynamische Halbleiterspeicheranordnung |
JP3464803B2 (ja) * | 1991-11-27 | 2003-11-10 | 株式会社東芝 | 半導体メモリセル |
US5220215A (en) * | 1992-05-15 | 1993-06-15 | Micron Technology, Inc. | Field programmable logic array with two or planes |
JP3302726B2 (ja) * | 1992-07-31 | 2002-07-15 | 株式会社東芝 | 半導体記憶装置 |
US5313433A (en) * | 1992-09-11 | 1994-05-17 | Micron Technology, Inc. | Windowed flash write circuit |
-
1994
- 1994-12-01 US US08/348,552 patent/US5513148A/en not_active Expired - Lifetime
-
1995
- 1995-11-30 EP EP95941501A patent/EP0744073B1/de not_active Expired - Lifetime
- 1995-11-30 AT AT95941501T patent/ATE216529T1/de not_active IP Right Cessation
- 1995-11-30 WO PCT/US1995/015558 patent/WO1996017355A1/en active IP Right Grant
- 1995-11-30 DE DE69526431T patent/DE69526431T2/de not_active Expired - Lifetime
- 1995-11-30 DE DE69535672T patent/DE69535672T2/de not_active Expired - Lifetime
- 1995-11-30 AU AU42902/96A patent/AU4290296A/en not_active Abandoned
- 1995-11-30 KR KR1019960704093A patent/KR100206063B1/ko not_active IP Right Cessation
- 1995-11-30 JP JP8519052A patent/JPH09507948A/ja active Pending
- 1995-11-30 EP EP01123861A patent/EP1191538B1/de not_active Expired - Lifetime
-
1996
- 1996-03-11 US US08/615,527 patent/US5666323A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1191538A1 (de) | 2002-03-27 |
EP0744073B1 (de) | 2002-04-17 |
DE69526431T2 (de) | 2002-12-12 |
DE69526431D1 (de) | 2002-05-23 |
US5513148A (en) | 1996-04-30 |
WO1996017355A1 (en) | 1996-06-06 |
ATE216529T1 (de) | 2002-05-15 |
AU4290296A (en) | 1996-06-19 |
KR100206063B1 (ko) | 1999-07-01 |
EP0744073A1 (de) | 1996-11-27 |
DE69535672T2 (de) | 2008-12-04 |
US5666323A (en) | 1997-09-09 |
JPH09507948A (ja) | 1997-08-12 |
EP1191538B1 (de) | 2007-12-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |