ATE216529T1 - Eine synchrone nand-dram-speicherarchitektur - Google Patents

Eine synchrone nand-dram-speicherarchitektur

Info

Publication number
ATE216529T1
ATE216529T1 AT95941501T AT95941501T ATE216529T1 AT E216529 T1 ATE216529 T1 AT E216529T1 AT 95941501 T AT95941501 T AT 95941501T AT 95941501 T AT95941501 T AT 95941501T AT E216529 T1 ATE216529 T1 AT E216529T1
Authority
AT
Austria
Prior art keywords
bank
memory
array
high speed
access
Prior art date
Application number
AT95941501T
Other languages
English (en)
Inventor
Paul Zagar
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE216529T1 publication Critical patent/ATE216529T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G11C11/4045—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell using a plurality of serially connected access transistors, each having a storage capacitor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
AT95941501T 1994-12-01 1995-11-30 Eine synchrone nand-dram-speicherarchitektur ATE216529T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/348,552 US5513148A (en) 1994-12-01 1994-12-01 Synchronous NAND DRAM architecture
PCT/US1995/015558 WO1996017355A1 (en) 1994-12-01 1995-11-30 A synchronous nand dram architecture

Publications (1)

Publication Number Publication Date
ATE216529T1 true ATE216529T1 (de) 2002-05-15

Family

ID=23368520

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95941501T ATE216529T1 (de) 1994-12-01 1995-11-30 Eine synchrone nand-dram-speicherarchitektur

Country Status (8)

Country Link
US (2) US5513148A (de)
EP (2) EP0744073B1 (de)
JP (1) JPH09507948A (de)
KR (1) KR100206063B1 (de)
AT (1) ATE216529T1 (de)
AU (1) AU4290296A (de)
DE (2) DE69526431T2 (de)
WO (1) WO1996017355A1 (de)

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US5675549A (en) * 1994-12-23 1997-10-07 Micron Technology, Inc. Burst EDO memory device address counter
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US6804760B2 (en) 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5682354A (en) * 1995-11-06 1997-10-28 Micron Technology, Inc. CAS recognition in burst extended data out DRAM
US5640364A (en) * 1994-12-23 1997-06-17 Micron Technology, Inc. Self-enabling pulse trapping circuit
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US5729504A (en) * 1995-12-14 1998-03-17 Micron Technology, Inc. Continuous burst edo memory device
US7681005B1 (en) * 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US6243768B1 (en) 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5926828A (en) * 1996-02-09 1999-07-20 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US6009038A (en) * 1996-05-31 1999-12-28 United Microelectronics Corporation Addressing unit
JPH09320269A (ja) * 1996-05-31 1997-12-12 Nippon Steel Corp アドレス装置
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US6981126B1 (en) * 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
US5784705A (en) * 1996-07-15 1998-07-21 Mosys, Incorporated Method and structure for performing pipeline burst accesses in a semiconductor memory
US5909225A (en) * 1997-05-30 1999-06-01 Hewlett-Packard Co. Frame buffer cache for graphics applications
US5937204A (en) * 1997-05-30 1999-08-10 Helwett-Packard, Co. Dual-pipeline architecture for enhancing the performance of graphics memory
US6002412A (en) * 1997-05-30 1999-12-14 Hewlett-Packard Co. Increased performance of graphics memory using page sorting fifos
KR100295641B1 (ko) * 1998-01-23 2001-08-07 김영환 글로벌워드라인드라이버
US6205482B1 (en) 1998-02-19 2001-03-20 Ameritech Corporation System and method for executing a request from a client application
US6199145B1 (en) * 1998-02-27 2001-03-06 Intel Corporation Configurable page closing method and apparatus for multi-port host bridges
KR100278658B1 (ko) * 1998-08-27 2001-01-15 윤종용 아날로그 펌핑 구조를 가지는 내부 클락 발생회로
TW459229B (en) 1999-02-24 2001-10-11 Matsushita Electric Ind Co Ltd Semiconductor memory device
US6609174B1 (en) * 1999-10-19 2003-08-19 Motorola, Inc. Embedded MRAMs including dual read ports
US6292387B1 (en) 2000-01-20 2001-09-18 Micron Technology, Inc. Selective device coupling
US6392935B1 (en) 2000-04-03 2002-05-21 Maxtor Corporation Maximum bandwidth/minimum latency SDRAM interface
KR100401508B1 (ko) * 2001-05-25 2003-10-17 주식회사 하이닉스반도체 램버스 디램의 뱅크 제어회로
US6779074B2 (en) * 2001-07-13 2004-08-17 Micron Technology, Inc. Memory device having different burst order addressing for read and write operations
US6590817B2 (en) 2001-07-23 2003-07-08 Micron Technology, Inc. 6F2 DRAM array with apparatus for stress testing an isolation gate and method
US7051264B2 (en) * 2001-11-14 2006-05-23 Monolithic System Technology, Inc. Error correcting memory and method of operating same
US7003644B2 (en) * 2002-03-28 2006-02-21 Seagate Technology Llc Execution time dependent command schedule optimization
US7457156B2 (en) * 2004-09-02 2008-11-25 Micron Technology, Inc. NAND flash depletion cell structure
US7392456B2 (en) * 2004-11-23 2008-06-24 Mosys, Inc. Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7539062B2 (en) 2006-12-20 2009-05-26 Micron Technology, Inc. Interleaved memory program and verify method, device and system
US8070965B2 (en) * 2007-04-18 2011-12-06 Tarves Robert J Jun Dual walled dynamic phase separator
CN102736860B (zh) * 2011-04-08 2015-03-11 安凯(广州)微电子技术有限公司 同步nand的数据操作系统及方法
CN110097917B (zh) * 2018-01-30 2021-03-30 长鑫存储技术有限公司 存储单元的电容测试装置、方法及半导体存储器
US10985162B2 (en) 2018-12-14 2021-04-20 John Bennett System for accurate multiple level gain cells
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Also Published As

Publication number Publication date
EP1191538A1 (de) 2002-03-27
EP0744073B1 (de) 2002-04-17
DE69526431T2 (de) 2002-12-12
DE69526431D1 (de) 2002-05-23
US5513148A (en) 1996-04-30
WO1996017355A1 (en) 1996-06-06
AU4290296A (en) 1996-06-19
KR100206063B1 (ko) 1999-07-01
EP0744073A1 (de) 1996-11-27
DE69535672D1 (de) 2008-01-31
DE69535672T2 (de) 2008-12-04
US5666323A (en) 1997-09-09
JPH09507948A (ja) 1997-08-12
EP1191538B1 (de) 2007-12-19

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