DE69519079T2 - Fabrikation einer integrierten Schaltung mit Zwillingswannen - Google Patents

Fabrikation einer integrierten Schaltung mit Zwillingswannen

Info

Publication number
DE69519079T2
DE69519079T2 DE69519079T DE69519079T DE69519079T2 DE 69519079 T2 DE69519079 T2 DE 69519079T2 DE 69519079 T DE69519079 T DE 69519079T DE 69519079 T DE69519079 T DE 69519079T DE 69519079 T2 DE69519079 T2 DE 69519079T2
Authority
DE
Germany
Prior art keywords
well
layer
substrate
fabrication
wells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69519079T
Other languages
German (de)
English (en)
Other versions
DE69519079D1 (de
Inventor
Kuo-Hua Lee
Chen-Hua Douglas Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69519079D1 publication Critical patent/DE69519079D1/de
Publication of DE69519079T2 publication Critical patent/DE69519079T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191—Manufacturing their doped wells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Element Separation (AREA)
DE69519079T 1994-12-08 1995-12-05 Fabrikation einer integrierten Schaltung mit Zwillingswannen Expired - Fee Related DE69519079T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35225794A 1994-12-08 1994-12-08

Publications (2)

Publication Number Publication Date
DE69519079D1 DE69519079D1 (de) 2000-11-16
DE69519079T2 true DE69519079T2 (de) 2001-03-15

Family

ID=23384405

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69519079T Expired - Fee Related DE69519079T2 (de) 1994-12-08 1995-12-05 Fabrikation einer integrierten Schaltung mit Zwillingswannen

Country Status (5)

Country Link
EP (1) EP0716443B1 (enExample)
JP (1) JP3300588B2 (enExample)
KR (1) KR100378448B1 (enExample)
DE (1) DE69519079T2 (enExample)
TW (1) TW288157B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100416002B1 (ko) 2001-08-31 2004-01-24 삼성전자주식회사 디스플레이장치의 다이나믹포커스 조정회로
KR100817417B1 (ko) * 2006-12-26 2008-03-27 동부일렉트로닉스 주식회사 고전압 씨모스 소자 및 그 제조 방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1213457B (it) * 1986-07-23 1989-12-20 Catania A Procedimento per la fabbricazione di dispositivi integrati, in particolare dispositivi cmos adoppia sacca.
GB8907897D0 (en) * 1989-04-07 1989-05-24 Inmos Ltd Forming wells in semiconductor devices

Also Published As

Publication number Publication date
TW288157B (enExample) 1996-10-11
JPH08222642A (ja) 1996-08-30
DE69519079D1 (de) 2000-11-16
EP0716443B1 (en) 2000-10-11
KR960026069A (ko) 1996-07-20
EP0716443A1 (en) 1996-06-12
JP3300588B2 (ja) 2002-07-08
KR100378448B1 (ko) 2003-06-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee