DE69508817T2 - Abscheidungsverfahren von Halbleiterschichten auf einem Träger - Google Patents

Abscheidungsverfahren von Halbleiterschichten auf einem Träger

Info

Publication number
DE69508817T2
DE69508817T2 DE69508817T DE69508817T DE69508817T2 DE 69508817 T2 DE69508817 T2 DE 69508817T2 DE 69508817 T DE69508817 T DE 69508817T DE 69508817 T DE69508817 T DE 69508817T DE 69508817 T2 DE69508817 T2 DE 69508817T2
Authority
DE
Germany
Prior art keywords
carrier
deposition process
semiconductor layers
semiconductor
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69508817T
Other languages
English (en)
Other versions
DE69508817D1 (de
Inventor
Michel Bruel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of DE69508817D1 publication Critical patent/DE69508817D1/de
Application granted granted Critical
Publication of DE69508817T2 publication Critical patent/DE69508817T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T225/00—Severing by tearing or breaking
    • Y10T225/10—Methods
    • Y10T225/12—With preliminary weakening
DE69508817T 1994-01-26 1995-01-24 Abscheidungsverfahren von Halbleiterschichten auf einem Träger Expired - Lifetime DE69508817T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9400836A FR2715501B1 (fr) 1994-01-26 1994-01-26 Procédé de dépôt de lames semiconductrices sur un support.

Publications (2)

Publication Number Publication Date
DE69508817D1 DE69508817D1 (de) 1999-05-12
DE69508817T2 true DE69508817T2 (de) 1999-10-07

Family

ID=9459420

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69508817T Expired - Lifetime DE69508817T2 (de) 1994-01-26 1995-01-24 Abscheidungsverfahren von Halbleiterschichten auf einem Träger

Country Status (5)

Country Link
US (1) US5559043A (de)
EP (1) EP0665588B1 (de)
JP (1) JP3905930B2 (de)
DE (1) DE69508817T2 (de)
FR (1) FR2715501B1 (de)

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FR2748850B1 (fr) 1996-05-15 1998-07-24 Commissariat Energie Atomique Procede de realisation d'un film mince de materiau solide et applications de ce procede
FR2748851B1 (fr) 1996-05-15 1998-08-07 Commissariat Energie Atomique Procede de realisation d'une couche mince de materiau semiconducteur
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US6372608B1 (en) * 1996-08-27 2002-04-16 Seiko Epson Corporation Separating method, method for transferring thin film device, thin film device, thin film integrated circuit device, and liquid crystal display device manufactured by using the transferring method
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US5759904A (en) * 1996-11-06 1998-06-02 Southwest Research Institute Suppression of transient enhanced diffusion in ion implanted silicon
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FR2756847B1 (fr) * 1996-12-09 1999-01-08 Commissariat Energie Atomique Procede de separation d'au moins deux elements d'une structure en contact entre eux par implantation ionique
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Also Published As

Publication number Publication date
EP0665588B1 (de) 1999-04-07
DE69508817D1 (de) 1999-05-12
FR2715501B1 (fr) 1996-04-05
US5559043A (en) 1996-09-24
JPH07254690A (ja) 1995-10-03
EP0665588A1 (de) 1995-08-02
JP3905930B2 (ja) 2007-04-18
FR2715501A1 (fr) 1995-07-28

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