DE69422229T2 - Verfahren zum Herstellen einer Halbleiterdünnschicht und Verfahren zur Herstellung einer Hall-Effekt-Anordnung - Google Patents

Verfahren zum Herstellen einer Halbleiterdünnschicht und Verfahren zur Herstellung einer Hall-Effekt-Anordnung

Info

Publication number
DE69422229T2
DE69422229T2 DE69422229T DE69422229T DE69422229T2 DE 69422229 T2 DE69422229 T2 DE 69422229T2 DE 69422229 T DE69422229 T DE 69422229T DE 69422229 T DE69422229 T DE 69422229T DE 69422229 T2 DE69422229 T2 DE 69422229T2
Authority
DE
Germany
Prior art keywords
producing
thin film
hall effect
semiconductor thin
effect arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69422229T
Other languages
English (en)
Other versions
DE69422229D1 (de
Inventor
Tetuo Kawasaki
Tetuhiro Koretika
Makoto Kitabatake
Takashi Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69422229D1 publication Critical patent/DE69422229D1/de
Publication of DE69422229T2 publication Critical patent/DE69422229T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02466—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02549—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/101—Semiconductor Hall-effect devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Hall/Mr Elements (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
DE69422229T 1993-05-28 1994-05-27 Verfahren zum Herstellen einer Halbleiterdünnschicht und Verfahren zur Herstellung einer Hall-Effekt-Anordnung Expired - Fee Related DE69422229T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP12692693 1993-05-28
JP14742293 1993-06-18
JP346294 1994-01-18

Publications (2)

Publication Number Publication Date
DE69422229D1 DE69422229D1 (de) 2000-01-27
DE69422229T2 true DE69422229T2 (de) 2000-05-11

Family

ID=27275846

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69422229T Expired - Fee Related DE69422229T2 (de) 1993-05-28 1994-05-27 Verfahren zum Herstellen einer Halbleiterdünnschicht und Verfahren zur Herstellung einer Hall-Effekt-Anordnung

Country Status (5)

Country Link
US (2) US5385864A (de)
EP (1) EP0632485B1 (de)
KR (1) KR100215588B1 (de)
CN (1) CN1059756C (de)
DE (1) DE69422229T2 (de)

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* Cited by examiner, † Cited by third party
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US5883564A (en) * 1994-04-18 1999-03-16 General Motors Corporation Magnetic field sensor having high mobility thin indium antimonide active layer on thin aluminum indium antimonide buffer layer
JP3537246B2 (ja) * 1995-11-14 2004-06-14 三菱電機株式会社 化合物半導体装置の製造方法
WO1998057360A1 (en) * 1997-06-13 1998-12-17 Northwestern University Long wavelength infrared photodetectors
TW444266B (en) * 1998-07-23 2001-07-01 Canon Kk Semiconductor substrate and method of producing same
US6630882B1 (en) * 1999-08-05 2003-10-07 Delphi Technologies, Inc. Composite magnetic sensor
JP3823693B2 (ja) * 2000-06-22 2006-09-20 株式会社村田製作所 半導体薄膜の製造方法およびその製造方法による半導体薄膜を備えた磁電変換素子
US6580139B1 (en) 2000-07-20 2003-06-17 Emcore Corporation Monolithically integrated sensing device and method of manufacture
CN100367526C (zh) * 2001-10-01 2008-02-06 旭化成电子材料元件株式会社 霍尔器件和磁传感器
JP4653397B2 (ja) * 2002-01-15 2011-03-16 旭化成エレクトロニクス株式会社 ホール素子の製造方法
US6985066B2 (en) * 2003-01-13 2006-01-10 Delphi Technologies, Inc. Controlled electron mobility galvanomagnetic devices
US7029995B2 (en) * 2003-06-13 2006-04-18 Asm America, Inc. Methods for depositing amorphous materials and using them as templates for epitaxial films by solid phase epitaxy
EP1647046A2 (de) * 2003-07-23 2006-04-19 ASM America, Inc. Ablagerung von sige auf silizium-auf-isolator-strukturen und bulk-substraten
WO2005086868A2 (en) * 2004-03-10 2005-09-22 Science & Technology Corporation @ Unm Metamorphic buffer on small lattice constant substrates
US7071103B2 (en) * 2004-07-30 2006-07-04 International Business Machines Corporation Chemical treatment to retard diffusion in a semiconductor overlayer
US7115955B2 (en) * 2004-07-30 2006-10-03 International Business Machines Corporation Semiconductor device having a strained raised source/drain
CN101331385B (zh) * 2005-12-16 2011-11-30 旭化成电子材料元件株式会社 位置检测装置
WO2007077865A1 (ja) * 2005-12-27 2007-07-12 Asahi Kasei Kabushiki Kaisha ＩｎＳｂ薄膜磁気センサ並びにその製造方法
US7847536B2 (en) * 2006-08-31 2010-12-07 Itron, Inc. Hall sensor with temperature drift control
EP2131398B1 (de) * 2007-03-23 2015-05-20 Asahi Kasei EMD Corporation Verbundhalbleiterlaminat, verfahren zur herstellung des verbundhalbleiterlaminats und halbleitervorrichtung
CN101805925B (zh) * 2010-02-20 2012-08-15 西安隆基硅材料股份有限公司 太阳能电池用掺镓铟单晶硅材料及其制备方法
JP6042077B2 (ja) * 2012-02-16 2016-12-14 旭化成エレクトロニクス株式会社 化合物半導体薄膜の製造方法
US20160035839A1 (en) * 2013-03-25 2016-02-04 Asahi Kasei Microdevices Corporation Compound semiconductor stack and semiconductor device
JP6233090B2 (ja) * 2014-02-21 2017-11-22 富士通株式会社 半導体装置
WO2016081313A1 (en) * 2014-11-18 2016-05-26 Sunedison Semiconductor Limited A method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers
CN111864056A (zh) * 2020-07-21 2020-10-30 浙江大学 一种铝掺锑化铟薄膜、磁阻传感元件及其制造方法
CN116963817A (zh) 2021-03-02 2023-10-27 株式会社力森诺科 氟化氢气体去除装置和氟化氢气体的去除方法
KR20230152694A (ko) 2021-03-02 2023-11-03 가부시끼가이샤 레조낙 불화수소 가스 제거 장치 및 불화수소 가스의 제거 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0272616A (ja) * 1988-09-07 1990-03-12 Fujitsu Ltd 分子線エピタキシャル成長法
FR2670693B1 (fr) * 1990-12-20 1993-04-16 Dutartre Didier Procede pour nettoyer la surface d'un substrat par plasma.
US5221637A (en) * 1991-05-31 1993-06-22 Interuniversitair Micro Elektronica Centrum Vzw Mesa release and deposition (MRD) method for stress relief in heteroepitaxially grown GaAs on Si
US5356509A (en) * 1992-10-16 1994-10-18 Astropower, Inc. Hetero-epitaxial growth of non-lattice matched semiconductors
US5275687A (en) * 1992-11-20 1994-01-04 At&T Bell Laboratories Process for removing surface contaminants from III-V semiconductors

Also Published As

Publication number Publication date
CN1059756C (zh) 2000-12-20
US5385864A (en) 1995-01-31
EP0632485A3 (de) 1995-08-23
EP0632485B1 (de) 1999-12-22
CN1098559A (zh) 1995-02-08
US5605860A (en) 1997-02-25
EP0632485A2 (de) 1995-01-04
KR100215588B1 (ko) 1999-08-16
DE69422229D1 (de) 2000-01-27

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee