DE69408763T2 - Digitale Verzögerungsleitung - Google Patents

Digitale Verzögerungsleitung

Info

Publication number
DE69408763T2
DE69408763T2 DE69408763T DE69408763T DE69408763T2 DE 69408763 T2 DE69408763 T2 DE 69408763T2 DE 69408763 T DE69408763 T DE 69408763T DE 69408763 T DE69408763 T DE 69408763T DE 69408763 T2 DE69408763 T2 DE 69408763T2
Authority
DE
Germany
Prior art keywords
delay line
digital delay
digital
line
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69408763T
Other languages
English (en)
Other versions
DE69408763D1 (de
Inventor
Jean-Luc Danger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Technology GmbH
STMicroelectronics SA
Original Assignee
Nokia Technology GmbH
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Technology GmbH, SGS Thomson Microelectronics SA filed Critical Nokia Technology GmbH
Application granted granted Critical
Publication of DE69408763D1 publication Critical patent/DE69408763D1/de
Publication of DE69408763T2 publication Critical patent/DE69408763T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
DE69408763T 1993-09-27 1994-09-21 Digitale Verzögerungsleitung Expired - Fee Related DE69408763T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9311750A FR2710800B1 (fr) 1993-09-27 1993-09-27 Ligne à retard numérique.

Publications (2)

Publication Number Publication Date
DE69408763D1 DE69408763D1 (de) 1998-04-09
DE69408763T2 true DE69408763T2 (de) 1998-06-25

Family

ID=9451477

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69408763T Expired - Fee Related DE69408763T2 (de) 1993-09-27 1994-09-21 Digitale Verzögerungsleitung

Country Status (5)

Country Link
US (2) US5633608A (de)
EP (1) EP0645888B1 (de)
JP (1) JP3613819B2 (de)
DE (1) DE69408763T2 (de)
FR (1) FR2710800B1 (de)

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DE10027703A1 (de) * 2000-06-03 2001-12-13 Sms Demag Ag Verfahren und Vorrichtung zum Umformen, insbesondere Fließpressen eines metallischen Werkstücks
US6420921B1 (en) 1999-05-17 2002-07-16 Advantest Corporation Delay signal generating apparatus and semiconductor test apparatus
DE10023483C2 (de) * 1999-05-10 2003-07-10 Advantest Corp Vorrichtung und Verfahren zum Einstellen der Verzögerung eines Eingangssignals

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US6239627B1 (en) * 1995-01-03 2001-05-29 Via-Cyrix, Inc. Clock multiplier using nonoverlapping clock pulses for waveform generation
JP3169794B2 (ja) * 1995-05-26 2001-05-28 日本電気株式会社 遅延クロック生成回路
JP3639000B2 (ja) * 1995-06-13 2005-04-13 富士通株式会社 位相合わせ装置及び遅延制御回路
FI100285B (fi) * 1995-12-11 1997-10-31 Nokia Mobile Phones Ltd Taajuudenmuodostuspiiri
KR100224718B1 (ko) * 1996-10-30 1999-10-15 윤종용 동기식 메모리장치의 내부 클락 발생기
US6044122A (en) * 1997-01-23 2000-03-28 Ericsson, Inc. Digital phase acquisition with delay locked loop
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
JP3319340B2 (ja) * 1997-05-30 2002-08-26 日本電気株式会社 半導体回路装置
US6205191B1 (en) * 1997-07-21 2001-03-20 Rambus Inc. Method and apparatus for synchronizing a control signal
US6150863A (en) * 1998-04-01 2000-11-21 Xilinx, Inc. User-controlled delay circuit for a programmable logic device
JP2002505836A (ja) * 1998-04-20 2002-02-19 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ タイミング回路
US6127858A (en) * 1998-04-30 2000-10-03 Intel Corporation Method and apparatus for varying a clock frequency on a phase by phase basis
KR20000045127A (ko) * 1998-12-30 2000-07-15 김영환 데이터 가변 지연회로
US6658581B1 (en) * 1999-03-29 2003-12-02 Agency Of Industrial Science & Technology Timing adjustment of clock signals in a digital circuit
US6259295B1 (en) * 1999-06-28 2001-07-10 Agere Systems Guardian Corp. Variable phase shifting clock generator
US7209178B1 (en) * 1999-09-21 2007-04-24 Samsung Electronics, Co., Ltd. Optical transfer system having a transmitter and a receiver
US6356132B1 (en) * 2000-01-31 2002-03-12 Agere Systems Guardian Corp. Programmable delay cell
JP2001255958A (ja) * 2000-03-10 2001-09-21 Konica Corp クロック発生装置、基板および画像形成装置ならびにクロック発生方法
US20010032323A1 (en) * 2000-04-06 2001-10-18 Konica Corporation Clock generating device
USRE41831E1 (en) 2000-05-23 2010-10-19 Marvell International Ltd. Class B driver
US7194037B1 (en) 2000-05-23 2007-03-20 Marvell International Ltd. Active replica transformer hybrid
US6775529B1 (en) 2000-07-31 2004-08-10 Marvell International Ltd. Active resistive summer for a transformer hybrid
US7433665B1 (en) 2000-07-31 2008-10-07 Marvell International Ltd. Apparatus and method for converting single-ended signals to a differential signal, and transceiver employing same
US7312739B1 (en) 2000-05-23 2007-12-25 Marvell International Ltd. Communication driver
JP3895520B2 (ja) * 2000-05-29 2007-03-22 富士通株式会社 クロック変調装置
US6377094B1 (en) * 2002-03-25 2002-04-23 Oak Technology, Inc. Arbitrary waveform synthesizer using a free-running ring oscillator
US7606547B1 (en) 2000-07-31 2009-10-20 Marvell International Ltd. Active resistance summer for a transformer hybrid
US6708238B1 (en) * 2001-01-19 2004-03-16 Sun Microsystems, Inc. Input/output cell with a programmable delay element
EP1410504A2 (de) * 2001-05-21 2004-04-21 Acuid Corporation Limited Programmierbares, selbstkalibrierendes verzögerungsfeinregelungssystem und verfahren dazu
US7333527B2 (en) * 2001-11-27 2008-02-19 Sun Microsystems, Inc. EMI reduction using tunable delay lines
TW558872B (en) * 2002-05-21 2003-10-21 Via Tech Inc Delay-locked loop device and method for generating clock signal
US20040225976A1 (en) * 2002-05-30 2004-11-11 Cheung Daniel Y. Glitch free programmable delay line for edge sensitive design
US7117382B2 (en) * 2002-05-30 2006-10-03 Sun Microsystems, Inc. Variably controlled delay line for read data capture timing window
US6856558B1 (en) 2002-09-20 2005-02-15 Integrated Device Technology, Inc. Integrated circuit devices having high precision digital delay lines therein
US7279938B1 (en) 2004-01-05 2007-10-09 Integrated Device Technology, Inc. Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein
US7109760B1 (en) 2004-01-05 2006-09-19 Integrated Device Technology, Inc. Delay-locked loop (DLL) integrated circuits that support efficient phase locking of clock signals having non-unity duty cycles
US7126404B1 (en) * 2004-01-20 2006-10-24 Marvell Semiconductor Israel Ltd. High resolution digital delay circuit for PLL and DLL
JP4143703B2 (ja) 2004-01-30 2008-09-03 テクトロニクス・インターナショナル・セールス・ゲーエムベーハー デジタル演算処理方法
US7440532B1 (en) 2004-04-21 2008-10-21 Altera Corporation Bit slip circuitry for serial data signals
KR100887016B1 (ko) * 2004-08-05 2009-03-04 마이크론 테크놀로지, 인크. 디지털 주파수 동기 지연선
US7664216B2 (en) * 2004-08-05 2010-02-16 Micron Technology, Inc. Digital frequency locked delay line
US7177775B2 (en) * 2005-04-29 2007-02-13 International Business Machines Corporation Testable digital delay line
US7312662B1 (en) 2005-08-09 2007-12-25 Marvell International Ltd. Cascode gain boosting system and method for a transmitter
US7577892B1 (en) 2005-08-25 2009-08-18 Marvell International Ltd High speed iterative decoder
US7464202B2 (en) * 2006-02-28 2008-12-09 Infineon Technologies Ag Clock system for controlling autonomous transfer of data
US7504872B2 (en) * 2007-08-13 2009-03-17 Nvidia Corporation Generic flexible timer design
US20100244921A1 (en) * 2009-03-31 2010-09-30 M2000 Sa. Programmable delay line circuit with glitch avoidance
KR101710669B1 (ko) 2010-09-15 2017-02-27 삼성전자주식회사 클록 지연 회로, 지연 동기 회로, 및 그것을 포함하는 반도체 메모리 장치
FR3024619B1 (fr) * 2014-08-01 2016-07-29 Pyxalis Circuit integre photorepete avec compensation des retards de propagation de signaux, notamment de signaux d'horloge

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JPS56157129A (en) * 1980-05-08 1981-12-04 Mitsubishi Electric Corp Priority selecting circuit
JPS59186415A (ja) * 1983-04-08 1984-10-23 テクトロニクス・インコ−ポレイテツド スキユ−検出器
JPS60219675A (ja) * 1984-04-13 1985-11-02 Sony Corp 時間軸変換回路
US4737670A (en) * 1984-11-09 1988-04-12 Lsi Logic Corporation Delay control circuit
SE449544B (sv) * 1985-09-06 1987-05-04 Ellemtel Utvecklings Ab Fasavstemningsanordning
US4755704A (en) * 1987-06-30 1988-07-05 Unisys Corporation Automatic clock de-skewing apparatus
US5043596A (en) * 1988-09-14 1991-08-27 Hitachi, Ltd. Clock signal supplying device having a phase compensation circuit
US5087829A (en) * 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
GB2234371A (en) * 1989-07-07 1991-01-30 Inmos Ltd Clock generation
US5077529A (en) * 1989-07-19 1991-12-31 Level One Communications, Inc. Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter
JPH0732389B2 (ja) * 1989-09-22 1995-04-10 日本電気株式会社 クロツクジツタ抑圧回路
US5258660A (en) * 1990-01-16 1993-11-02 Cray Research, Inc. Skew-compensated clock distribution system
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
DE4004195C2 (de) * 1990-02-12 1996-10-02 Broadcast Television Syst Schaltungsanordnung zur Erzeugung eines mit einem Referenzsignal verkoppelten Signals
US5118975A (en) * 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
US5210450A (en) * 1990-04-16 1993-05-11 Tektronix, Inc. Active selectable digital delay circuit
US5272729A (en) * 1991-09-20 1993-12-21 International Business Machines Corporation Clock signal latency elimination network
US5146121A (en) * 1991-10-24 1992-09-08 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
US5534808A (en) * 1992-01-31 1996-07-09 Konica Corporation Signal delay method, signal delay device and circuit for use in the apparatus
US5281874A (en) * 1992-02-14 1994-01-25 Vlsi Technology, Inc. Compensated digital delay semiconductor device with selectable output taps and method therefor
US5252867A (en) * 1992-02-14 1993-10-12 Vlsi Technology, Inc. Self-compensating digital delay semiconductor device with selectable output delays and method therefor
US5250913A (en) * 1992-02-21 1993-10-05 Advanced Micro Devices, Inc. Variable pulse width phase detector
US5191295A (en) * 1992-03-11 1993-03-02 Ltx Corporation Phase shift vernier for automatic test systems
US5365130A (en) * 1992-08-07 1994-11-15 Vlsi Technology, Inc. Self-compensating output pad for an integrated circuit and method therefor
US5521499A (en) * 1992-12-23 1996-05-28 Comstream Corporation Signal controlled phase shifter
US5552733A (en) * 1993-01-19 1996-09-03 Credence Systems Corporation Precise and agile timing signal generator based on a retriggered oscillator
SE500929C2 (sv) * 1993-02-24 1994-10-03 Ellemtel Utvecklings Ab Signalbehandlingskrets och förfarande för fördröjning av en binär periodisk insignal

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10023483C2 (de) * 1999-05-10 2003-07-10 Advantest Corp Vorrichtung und Verfahren zum Einstellen der Verzögerung eines Eingangssignals
US6651179B1 (en) 1999-05-10 2003-11-18 Advantest Corporation Delay time judging apparatus
US6420921B1 (en) 1999-05-17 2002-07-16 Advantest Corporation Delay signal generating apparatus and semiconductor test apparatus
DE10024640B4 (de) * 1999-05-17 2006-01-12 Advantest Corp. Verzögerungssignal-Erzeugungsvorrichtung und Halbleiterprüfvorrichtung
DE10027703A1 (de) * 2000-06-03 2001-12-13 Sms Demag Ag Verfahren und Vorrichtung zum Umformen, insbesondere Fließpressen eines metallischen Werkstücks
DE10027703B4 (de) * 2000-06-03 2005-03-03 Sms Demag Ag Verfahren und Vorrichtung zum Umformen, insbesondere Fließpressen eines metallischen Werkstücks

Also Published As

Publication number Publication date
EP0645888A1 (de) 1995-03-29
US5633608A (en) 1997-05-27
US5719515A (en) 1998-02-17
JP3613819B2 (ja) 2005-01-26
EP0645888B1 (de) 1998-03-04
DE69408763D1 (de) 1998-04-09
JPH07202657A (ja) 1995-08-04
FR2710800A1 (fr) 1995-04-07
FR2710800B1 (fr) 1995-12-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee