DE69333078D1 - Halbleiterwafer mit geringer Oberflächenrauhigkeit und Halbleiterbauelement - Google Patents

Halbleiterwafer mit geringer Oberflächenrauhigkeit und Halbleiterbauelement

Info

Publication number
DE69333078D1
DE69333078D1 DE69333078T DE69333078T DE69333078D1 DE 69333078 D1 DE69333078 D1 DE 69333078D1 DE 69333078 T DE69333078 T DE 69333078T DE 69333078 T DE69333078 T DE 69333078T DE 69333078 D1 DE69333078 D1 DE 69333078D1
Authority
DE
Germany
Prior art keywords
surface roughness
low surface
semiconductor device
semiconductor
semiconductor wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69333078T
Other languages
English (en)
Other versions
DE69333078T2 (de
Inventor
Mamoru Miyawaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69333078D1 publication Critical patent/DE69333078D1/de
Publication of DE69333078T2 publication Critical patent/DE69333078T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Weting (AREA)
  • Recrystallisation Techniques (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69333078T 1992-01-31 1993-01-29 Halbleiterwafer mit geringer Oberflächenrauhigkeit und Halbleiterbauelement Expired - Fee Related DE69333078T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP01674592A JP3187109B2 (ja) 1992-01-31 1992-01-31 半導体部材およびその製造方法
JP1674592 1992-01-31

Publications (2)

Publication Number Publication Date
DE69333078D1 true DE69333078D1 (de) 2003-08-14
DE69333078T2 DE69333078T2 (de) 2004-05-27

Family

ID=11924810

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69333078T Expired - Fee Related DE69333078T2 (de) 1992-01-31 1993-01-29 Halbleiterwafer mit geringer Oberflächenrauhigkeit und Halbleiterbauelement

Country Status (4)

Country Link
US (1) US5543648A (de)
EP (2) EP0553861B1 (de)
JP (1) JP3187109B2 (de)
DE (1) DE69333078T2 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07144999A (ja) * 1993-11-22 1995-06-06 Denki Kagaku Kogyo Kk 針状単結晶体及びその製法
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
DE4420024C2 (de) * 1994-06-09 1996-05-30 Heraeus Quarzglas Halbzeug in Form eines Verbundkörpers für ein elektronisches oder opto-elektronisches Halbleiterbauelement
US6228751B1 (en) * 1995-09-08 2001-05-08 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP3040067B2 (ja) * 1995-09-28 2000-05-08 ローム株式会社 半導体層を有する基板の洗浄方法
EP0797243A3 (de) * 1996-03-07 1999-06-16 Texas Instruments Incorporated Ätzverfahren für dielektrische Schichten in Halbleiterschaltungen
AU3137097A (en) 1996-05-16 1997-12-05 Lockheed Martin Energy Systems, Inc. Low temperature material bonding technique
US6287900B1 (en) * 1996-08-13 2001-09-11 Semiconductor Energy Laboratory Co., Ltd Semiconductor device with catalyst addition and removal
JP3647191B2 (ja) 1997-03-27 2005-05-11 キヤノン株式会社 半導体装置の製造方法
JP3211872B2 (ja) * 1997-07-29 2001-09-25 日本電気株式会社 薬液処理方法、半導体基板の処理方法及び半導体装置の製造方法
US6165873A (en) * 1998-11-27 2000-12-26 Nec Corporation Process for manufacturing a semiconductor integrated circuit device
JP2000173976A (ja) * 1998-12-02 2000-06-23 Mitsubishi Electric Corp 半導体装置の製造方法
JP2000223682A (ja) * 1999-02-02 2000-08-11 Canon Inc 基体の処理方法及び半導体基板の製造方法
AT409429B (de) * 1999-07-15 2002-08-26 Sez Semiconduct Equip Zubehoer Verfahren zum ätzbehandeln von halbleitersubstraten zwecks freilegen einer metallschicht
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6652972B1 (en) 1999-11-01 2003-11-25 Schott Glass Technologies Inc. Low temperature joining of phosphate glass
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
AU2001273599A1 (en) 2000-06-20 2002-01-02 Schott Glass Technologies, Inc. Glass ceramic composites
US6555487B1 (en) 2000-08-31 2003-04-29 Micron Technology, Inc. Method of selective oxidation conditions for dielectric conditioning
US6882782B2 (en) * 2000-11-01 2005-04-19 Schott Glas Photonic devices for optical and optoelectronic information processing
US6699770B2 (en) * 2001-03-01 2004-03-02 John Tarje Torvik Method of making a hybride substrate having a thin silicon carbide membrane layer
JP2001358089A (ja) * 2001-05-10 2001-12-26 Oki Electric Ind Co Ltd 半導体装置の製造方法
US7449682B2 (en) * 2001-10-26 2008-11-11 Revera Incorporated System and method for depth profiling and characterization of thin films
JP4694782B2 (ja) * 2002-12-02 2011-06-08 財団法人国際科学振興財団 半導体装置、その製造方法、及び、半導体表面の処理方法
AU2003264642B2 (en) 2002-12-02 2009-08-06 Tadahiro Ohmi Semiconductor Device and Method of Manufacturing the Same
US6800852B2 (en) * 2002-12-27 2004-10-05 Revera Incorporated Nondestructive characterization of thin films using measured basis spectra
US6891158B2 (en) * 2002-12-27 2005-05-10 Revera Incorporated Nondestructive characterization of thin films based on acquired spectrum
JP2004281878A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体基板の製造方法及びこれにより製造される半導体基板、電気光学装置並びに電子機器
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
FR2868599B1 (fr) 2004-03-30 2006-07-07 Soitec Silicon On Insulator Traitement chimique optimise de type sc1 pour le nettoyage de plaquettes en materiau semiconducteur
JPWO2006009003A1 (ja) * 2004-07-16 2008-05-01 国立大学法人東北大学 半導体装置の処理液、処理方法および半導体製造装置
FR2880185B1 (fr) * 2004-12-24 2007-07-20 Soitec Silicon On Insulator Procede de traitement d'une surface de plaquette
FR2880186B1 (fr) * 2004-12-24 2007-07-20 Soitec Silicon On Insulator Procede de traitement d'une surface de plaquette
US7919391B2 (en) * 2004-12-24 2011-04-05 S.O.I.Tec Silicon On Insulator Technologies Methods for preparing a bonding surface of a semiconductor wafer
US20090130816A1 (en) * 2005-07-22 2009-05-21 Sumco Corporation Method for manufacturing simox wafer and simox wafer manufactured thereby
US7888197B2 (en) * 2007-01-11 2011-02-15 International Business Machines Corporation Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer
US8778816B2 (en) * 2011-02-04 2014-07-15 Applied Materials, Inc. In situ vapor phase surface activation of SiO2
DE102011014845B4 (de) * 2011-03-23 2023-05-17 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Licht emittierendes Halbleiterbauteil und Verfahren zur Herstellung eines Licht emittierenden Halbleiterbauteils

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3612960A (en) * 1968-10-15 1971-10-12 Tokyo Shibaura Electric Co Semiconductor device
US4278987A (en) * 1977-10-17 1981-07-14 Hitachi, Ltd. Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations
JP2680482B2 (ja) * 1990-06-25 1997-11-19 株式会社東芝 半導体基板、半導体基板と半導体装置の製造方法、並びに半導体基板の検査・評価方法
JPS61193456A (ja) * 1985-02-21 1986-08-27 Toshiba Corp 半導体素子の製造方法
EP0348757B1 (de) * 1988-06-28 1995-01-04 Mitsubishi Materials Silicon Corporation Verfahren zur Polierung eines Halbleiter-Plättchens
US5230768A (en) * 1990-03-26 1993-07-27 Sharp Kabushiki Kaisha Method for the production of SiC single crystals by using a specific substrate crystal orientation
JP3437195B2 (ja) * 1991-10-01 2003-08-18 キヤノン株式会社 Ｍｉｍ型電気素子とその製造方法、及びこれを用いた画像表示装置、描画装置
JPH06263595A (ja) * 1993-03-10 1994-09-20 Canon Inc ダイヤモンド被覆部材及びその製造方法

Also Published As

Publication number Publication date
JP3187109B2 (ja) 2001-07-11
DE69333078T2 (de) 2004-05-27
EP0553861A1 (de) 1993-08-04
EP0553861B1 (de) 2003-07-09
EP0828289A1 (de) 1998-03-11
JPH05217981A (ja) 1993-08-27
US5543648A (en) 1996-08-06

Similar Documents

Publication Publication Date Title
DE69333078D1 (de) Halbleiterwafer mit geringer Oberflächenrauhigkeit und Halbleiterbauelement
DE69323127D1 (de) Halbleitervorrichtung und Herstellungsverfahren
KR910007164A (ko) 반도체장치 및 그 제조방법
KR900019215A (ko) 반도체장치 및 그의 제조방법
DE69435205D1 (de) Dünne Halbleitervorrichtung und Herstellungsverfahren
GB8907898D0 (en) Semiconductor devices and fabrication thereof
DE69421248D1 (de) Polierteil und Wafer-Poliervorrichtung
KR910008793A (ko) 반도체장치 및 그 제조방법
DE68928448D1 (de) Halbleitervorrichtung und Herstellungsverfahren
EP0506980A4 (en) Structure of semiconductor device and manufacturing method thereof
ITRM920518A0 (it) Dispositivo a semiconduttore controllabile con limitazione di correnteintegrata e diseccitazione in caso di sovratemperatura
EP0452950A3 (en) Semiconductor device using whiskers and manufacturing method of the same
DE69430511D1 (de) Halbleiteranordnung und Herstellungverfahren
KR910003787A (ko) 반도체장치 및 반도체장치의 제조방법
DE69413602D1 (de) Halbleiteranordnung und Herstellungsverfahren
DE69325343D1 (de) Halbleiteranordnung und Herstellungsverfahren dafür
EP0341821A3 (en) Semiconductor device and method of manufacturing the same
DE68919485D1 (de) Halbleitersubstrat mit Substratscheibe und Verbindungshalbleiterschicht.
EP0450558A3 (en) Semiconductor device and method of manufacturing the same
HK1009308A1 (en) Semi-conductor device and method of manufacturing the same
EP0410737A3 (en) Silicon crystal evaluation method and semiconductor device fabrication method using the same
KR910010691A (ko) 반도체장치의 배선접촉구조 및 그 제조방법
KR900017121A (ko) 패턴오염으로부터 보호되는 반도체장치 및 그의 제조방법
DE3856248D1 (de) Siliciumwafer-handhabungssystem mit bernoulli-aufnahme
KR890013797A (ko) 반도체장치와 그 사용방법

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee