DE69327434T2 - Dünnschicht-Halbleiteranordnung und Verfahren zu ihrer Herstellung - Google Patents

Dünnschicht-Halbleiteranordnung und Verfahren zu ihrer Herstellung

Info

Publication number
DE69327434T2
DE69327434T2 DE69327434T DE69327434T DE69327434T2 DE 69327434 T2 DE69327434 T2 DE 69327434T2 DE 69327434 T DE69327434 T DE 69327434T DE 69327434 T DE69327434 T DE 69327434T DE 69327434 T2 DE69327434 T2 DE 69327434T2
Authority
DE
Germany
Prior art keywords
thin
production
semiconductor device
film semiconductor
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69327434T
Other languages
English (en)
Other versions
DE69327434D1 (de
Inventor
Katsuki Matsushita
Shigeru Senbonmatsu
Tsuneo Yamazaki
Tadao Iwaki
Ryuichi Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Application granted granted Critical
Publication of DE69327434D1 publication Critical patent/DE69327434D1/de
Publication of DE69327434T2 publication Critical patent/DE69327434T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
DE69327434T 1992-08-26 1993-08-26 Dünnschicht-Halbleiteranordnung und Verfahren zu ihrer Herstellung Expired - Fee Related DE69327434T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22764592A JPH0677447A (ja) 1992-08-26 1992-08-26 半導体薄膜素子の製造方法

Publications (2)

Publication Number Publication Date
DE69327434D1 DE69327434D1 (de) 2000-02-03
DE69327434T2 true DE69327434T2 (de) 2000-05-11

Family

ID=16864125

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327434T Expired - Fee Related DE69327434T2 (de) 1992-08-26 1993-08-26 Dünnschicht-Halbleiteranordnung und Verfahren zu ihrer Herstellung

Country Status (5)

Country Link
US (1) US5459335A (de)
EP (1) EP0585125B1 (de)
JP (1) JPH0677447A (de)
KR (1) KR940004849A (de)
DE (1) DE69327434T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5603779A (en) * 1995-05-17 1997-02-18 Harris Corporation Bonded wafer and method of fabrication thereof
US6132798A (en) * 1998-08-13 2000-10-17 Micron Technology, Inc. Method for applying atomized adhesive to a leadframe for chip bonding
US6030857A (en) * 1996-03-11 2000-02-29 Micron Technology, Inc. Method for application of spray adhesive to a leadframe for chip bonding
US5810926A (en) * 1996-03-11 1998-09-22 Micron Technology, Inc. Method and apparatus for applying atomized adhesive to a leadframe for chip bonding
KR100420213B1 (ko) * 2001-05-07 2004-03-04 산양전기주식회사 연성인쇄회로기판용 점착성도료와 그 사용방법
US8415208B2 (en) 2001-07-16 2013-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and peeling off method and method of manufacturing semiconductor device
US6934001B2 (en) * 2001-08-13 2005-08-23 Sharp Laboratories Of America, Inc. Structure and method for supporting a flexible substrate
US20030161044A1 (en) * 2002-02-04 2003-08-28 Nikon Corporation Diffractive optical element and method for manufacturing same
JP3983681B2 (ja) * 2003-01-14 2007-09-26 株式会社マキタ 充電装置
TWI223428B (en) * 2003-11-13 2004-11-01 United Microelectronics Corp Frame attaching process
DE102004029765A1 (de) * 2004-06-21 2006-03-16 Infineon Technologies Ag Substratbasiertes Die-Package mit BGA- oder BGA-ähnlichen Komponenten
JP5565198B2 (ja) * 2010-08-19 2014-08-06 株式会社島津製作所 回路構成体の接着剤注入装置および回路構成体の接着剤注入方法
JP5561018B2 (ja) * 2010-08-19 2014-07-30 株式会社島津製作所 接着剤注入装置および接着剤注入方法
KR20150120376A (ko) 2013-02-20 2015-10-27 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박리 방법, 반도체 장치, 및 박리 장치
WO2015087192A1 (en) 2013-12-12 2015-06-18 Semiconductor Energy Laboratory Co., Ltd. Peeling method and peeling apparatus
KR102520709B1 (ko) 2016-04-19 2023-04-12 삼성디스플레이 주식회사 인쇄회로기판용 보호테이프 및 이를 구비하는 디스플레이 장치

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4070230A (en) * 1974-07-04 1978-01-24 Siemens Aktiengesellschaft Semiconductor component with dielectric carrier and its manufacture
US4266334A (en) * 1979-07-25 1981-05-12 Rca Corporation Manufacture of thinned substrate imagers
JPS6123379A (ja) * 1984-07-11 1986-01-31 Hitachi Ltd 光電子装置
US4599970A (en) * 1985-03-11 1986-07-15 Rca Corporation Apparatus for coating a selected area of the surface of an object
JPS63308386A (ja) * 1987-01-30 1988-12-15 Sony Corp 半導体装置とその製造方法
US4888364A (en) * 1989-01-26 1989-12-19 Dow Corning Corporation Solid gel dispensers for achieving controlled release of volatile liquid materials and method for preparing same
US5034801A (en) * 1989-07-31 1991-07-23 W. L. Gore & Associates, Inc. Intergrated circuit element having a planar, solvent-free dielectric layer
US5121190A (en) * 1990-03-14 1992-06-09 International Business Machines Corp. Solder interconnection structure on organic substrates
JP2927982B2 (ja) * 1991-03-18 1999-07-28 ジャパンゴアテックス株式会社 半導体装置

Also Published As

Publication number Publication date
EP0585125A2 (de) 1994-03-02
EP0585125A3 (en) 1997-09-10
US5459335A (en) 1995-10-17
JPH0677447A (ja) 1994-03-18
EP0585125B1 (de) 1999-12-29
DE69327434D1 (de) 2000-02-03
KR940004849A (ko) 1994-03-16

Similar Documents

Publication Publication Date Title
DE4323799B4 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE69309583D1 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE69329635D1 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE69333294D1 (de) Halbleiteranordnung und Verfahren zu seiner Herstellung
DE69231290D1 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE3855765D1 (de) Dünnschicht-Siliciumhalbleiteranordnung und Verfahren zu ihrer Herstellung
DE68926645D1 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE69030822T2 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE69532907D1 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE69306115T2 (de) Elektrolumineszierende vorrichtungen und verfahren zu ihrer herstellung
DE69637701D1 (de) Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE69313024D1 (de) Festkörperbildaufnahmeanordnung und Verfahren zu ihrer Herstellung
DE69327860D1 (de) Verbindungshalbleiterbauelement und Verfahren zu seiner Herstellung
DE69226488D1 (de) Halbleiterspeicheranordnung und Verfahren zu ihrer Herstellung
DE69327434T2 (de) Dünnschicht-Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE19651550B8 (de) Halbleitervorrichtung und Verfahren zu deren Herstellung
DE69306678D1 (de) Dichtungsvorrichtung und Verfahren zu ihrer Herstellung
DE69637578D1 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE69223539D1 (de) Dünnschicht-Halbleiter-Vorrichtung und Verfahren zu deren Herstellung
DE69330302D1 (de) Halbleiterspeicheranordnung und Verfahren zu ihrer Herstellung
DE69128963T2 (de) Halbleitervorrichtung und Verfahren zu seiner Herstellung
DE69219100D1 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE69531127D1 (de) Halbleitervorrichtung und Verfahren zu deren Herstellung
DE69033662T2 (de) Integrierte Halbleitervorrichtung und Verfahren zu ihrer Herstellung
DE69232472D1 (de) MOS-Halbleiteranordnung und Verfahren zu ihrer Herstellung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee