DE69325065D1 - Halbleitervorrichtung, Bildabtastvorrichtung und Verfahren zu ihrer Herstellung - Google Patents

Halbleitervorrichtung, Bildabtastvorrichtung und Verfahren zu ihrer Herstellung

Info

Publication number
DE69325065D1
DE69325065D1 DE69325065T DE69325065T DE69325065D1 DE 69325065 D1 DE69325065 D1 DE 69325065D1 DE 69325065 T DE69325065 T DE 69325065T DE 69325065 T DE69325065 T DE 69325065T DE 69325065 D1 DE69325065 D1 DE 69325065D1
Authority
DE
Germany
Prior art keywords
manufacturing
semiconductor device
same
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Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69325065T
Other languages
English (en)
Other versions
DE69325065T2 (de
Inventor
Tetsuro Nakamura
Eiichiro Tanaka
Shinji Fujiwara
Masahiro Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69325065D1 publication Critical patent/DE69325065D1/de
Publication of DE69325065T2 publication Critical patent/DE69325065T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0203—Containers; Encapsulations, e.g. encapsulation of photodiodes
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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    • H01L2224/832—Applying energy for connecting
    • H01L2224/8322—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/83224—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
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    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Solid State Image Pick-Up Elements (AREA)
DE69325065T 1992-10-02 1993-10-01 Halbleitervorrichtung, Bildabtastvorrichtung und Verfahren zu ihrer Herstellung Expired - Fee Related DE69325065T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP26451292 1992-10-02
JP13822193 1993-06-10

Publications (2)

Publication Number Publication Date
DE69325065D1 true DE69325065D1 (de) 1999-07-01
DE69325065T2 DE69325065T2 (de) 1999-10-28

Family

ID=26471329

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69325065T Expired - Fee Related DE69325065T2 (de) 1992-10-02 1993-10-01 Halbleitervorrichtung, Bildabtastvorrichtung und Verfahren zu ihrer Herstellung

Country Status (3)

Country Link
US (2) US5408121A (de)
EP (1) EP0591862B1 (de)
DE (1) DE69325065T2 (de)

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EP0657932B1 (de) * 1993-12-13 2001-09-05 Matsushita Electric Industrial Co., Ltd. Vorrichtung mit Chipgehäuse und Verfahren zu Ihrer Herstellung
JP3030201B2 (ja) * 1994-04-26 2000-04-10 富士通株式会社 半導体装置の製造方法及び半導体装置の製造装置
US5976955A (en) * 1995-01-04 1999-11-02 Micron Technology, Inc. Packaging for bare dice employing EMR-sensitive adhesives
JP3285294B2 (ja) * 1995-08-08 2002-05-27 太陽誘電株式会社 回路モジュールの製造方法
DE19606101A1 (de) * 1996-02-19 1997-08-21 Siemens Ag Halbleiterkörper mit Lotmaterialschicht
US5726079A (en) * 1996-06-19 1998-03-10 International Business Machines Corporation Thermally enhanced flip chip package and method of forming
USRE39426E1 (en) * 1996-06-19 2006-12-12 International Business Machines Corporation Thermally enhanced flip chip package and method of forming
JPH1032223A (ja) * 1996-07-15 1998-02-03 Mitsubishi Electric Corp 半導体装置
JP3431406B2 (ja) * 1996-07-30 2003-07-28 株式会社東芝 半導体パッケージ装置
EP0824301A3 (de) * 1996-08-09 1999-08-11 Hitachi, Ltd. Gedruckte Schaltungsplatte, Chipkarte, und Verfahren zu deren Herstellung
DE19643911A1 (de) * 1996-10-30 1998-05-07 Sick Ag Schaltungsanordnung mit auf einem mit Leiterbahnen versehenen Substrat angebrachten optoelektronischen Bauelementen
US6495083B2 (en) * 1997-10-29 2002-12-17 Hestia Technologies, Inc. Method of underfilling an integrated circuit chip
US6324069B1 (en) 1997-10-29 2001-11-27 Hestia Technologies, Inc. Chip package with molded underfill
US6038136A (en) * 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
US6028773A (en) * 1997-11-14 2000-02-22 Stmicroelectronics, Inc. Packaging for silicon sensors
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US5408121A (en) 1995-04-18

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