DE69308804T2 - Testverfahren für Elemente von integrierten Schaltungen und dazugehöriges integriertes Element - Google Patents

Testverfahren für Elemente von integrierten Schaltungen und dazugehöriges integriertes Element

Info

Publication number
DE69308804T2
DE69308804T2 DE69308804T DE69308804T DE69308804T2 DE 69308804 T2 DE69308804 T2 DE 69308804T2 DE 69308804 T DE69308804 T DE 69308804T DE 69308804 T DE69308804 T DE 69308804T DE 69308804 T2 DE69308804 T2 DE 69308804T2
Authority
DE
Germany
Prior art keywords
test
demultiplexer
wafer
chips
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69308804T
Other languages
English (en)
Other versions
DE69308804D1 (de
Inventor
Francois Tailliet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE69308804D1 publication Critical patent/DE69308804D1/de
Publication of DE69308804T2 publication Critical patent/DE69308804T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
DE69308804T 1992-12-31 1993-12-27 Testverfahren für Elemente von integrierten Schaltungen und dazugehöriges integriertes Element Expired - Fee Related DE69308804T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9215997A FR2700063B1 (fr) 1992-12-31 1992-12-31 Procédé de test de puces de circuit intégré et dispositif intégré correspondant.

Publications (2)

Publication Number Publication Date
DE69308804D1 DE69308804D1 (de) 1997-04-17
DE69308804T2 true DE69308804T2 (de) 1997-06-19

Family

ID=9437350

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69308804T Expired - Fee Related DE69308804T2 (de) 1992-12-31 1993-12-27 Testverfahren für Elemente von integrierten Schaltungen und dazugehöriges integriertes Element

Country Status (5)

Country Link
US (1) US5608335A (de)
EP (1) EP0606805B1 (de)
JP (1) JPH0737947A (de)
DE (1) DE69308804T2 (de)
FR (1) FR2700063B1 (de)

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DE19936321C2 (de) * 1999-08-02 2003-12-24 Infineon Technologies Ag Anordnung und Verfahren zum Testen einer Vielzahl von Halbleiterchips auf Waferebene

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US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US6046600A (en) * 1995-10-31 2000-04-04 Texas Instruments Incorporated Process of testing integrated circuit dies on a wafer
JPH1070243A (ja) * 1996-05-30 1998-03-10 Toshiba Corp 半導体集積回路装置およびその検査方法およびその検査装置
US6750527B1 (en) * 1996-05-30 2004-06-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method
JP3696352B2 (ja) * 1996-12-17 2005-09-14 三菱電機株式会社 ライフタイム評価用ｔｅｇ
US6121065A (en) * 1997-09-26 2000-09-19 Institute Of Microelectronics Wafer scale burn-in testing
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
DE19808664C2 (de) * 1998-03-02 2002-03-14 Infineon Technologies Ag Integrierte Schaltung und Verfahren zu ihrer Prüfung
DE19819570C2 (de) * 1998-04-30 2000-06-15 Siemens Ag Anordnung zum Testen mehrerer Speicherchips auf einem Wafer
US6233184B1 (en) * 1998-11-13 2001-05-15 International Business Machines Corporation Structures for wafer level test and burn-in
US6140833A (en) * 1998-11-16 2000-10-31 Siemens Aktiengesellschaft In-situ measurement method and apparatus for semiconductor processing
JP3484365B2 (ja) * 1999-01-19 2004-01-06 シャープ株式会社 半導体装置用パッケージ、この半導体装置用パッケージのテスト時に使用するプローブカード、および、このプローブカードを用いたパッケージのテスト方法
US7058862B2 (en) * 2000-05-26 2006-06-06 Texas Instruments Incorporated Selecting different 1149.1 TAP domains from update-IR state
JP3483130B2 (ja) * 1999-11-29 2004-01-06 松下電器産業株式会社 集積回路の検査方法
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
US6603323B1 (en) * 2000-07-10 2003-08-05 Formfactor, Inc. Closed-grid bus architecture for wafer interconnect structure
JP4170220B2 (ja) * 2001-09-28 2008-10-22 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 集積回路を製造する方法と、この方法によって得られる集積回路と、この方法によって得られる集積回路が設けられているウェハと、この方法によって得られる集積回路を有するシステム
US20040051550A1 (en) * 2002-09-12 2004-03-18 Ma David Suitwai Semiconductor die isolation system
DE102004001956B4 (de) * 2004-01-13 2007-02-01 Infineon Technologies Ag Umverdrahtungssubstratstreifen mit mehreren Halbleiterbauteilpositionen
US7307433B2 (en) * 2004-04-21 2007-12-11 Formfactor, Inc. Intelligent probe card architecture
DE102005034494A1 (de) * 2005-07-20 2007-01-25 Endress + Hauser Conducta Gesellschaft für Mess- und Regeltechnik mbH + Co. KG Verfahren zur Herstellung von Speichermodulen
KR100636502B1 (ko) * 2005-08-31 2006-10-18 삼성에스디아이 주식회사 원장단위 검사가 가능한 유기 전계발광표시장치 및 그검사방법
KR100754140B1 (ko) * 2005-12-21 2007-08-31 삼성에스디아이 주식회사 원장단위 검사가 가능한 유기 발광 표시장치 및 모기판과그 검사방법
US7405585B2 (en) * 2006-02-14 2008-07-29 Taiwan Semiconductor Manufacturing Co., Ltd. Versatile semiconductor test structure array
KR100759688B1 (ko) * 2006-04-07 2007-09-17 삼성에스디아이 주식회사 원장단위 검사가 가능한 유기전계발광 표시장치 및모기판과 그 검사방법
KR100793558B1 (ko) * 2006-09-18 2008-01-14 삼성에스디아이 주식회사 유기전계발광 표시장치 및 그의 모기판과 유기전계발광표시장치의 제조방법
US7719299B2 (en) * 2008-04-02 2010-05-18 Texas Instruments Incorporated Process and temperature insensitive flicker noise monitor circuit
JP5412667B2 (ja) * 2008-12-26 2014-02-12 独立行政法人産業技術総合研究所 積層ｌｓｉチップのシステム検査のための方法および検査システム
USD751555S1 (en) * 2013-03-05 2016-03-15 Japan Electronic Materials Corp. Probe card case
KR102047005B1 (ko) * 2013-05-31 2019-11-21 삼성디스플레이 주식회사 유기 발광 표시 패널
CN105788510A (zh) * 2014-12-17 2016-07-20 昆山国显光电有限公司 Oled显示装置及其老化方法
CN105632383B (zh) 2016-01-11 2018-09-11 京东方科技集团股份有限公司 一种测试电路、测试方法、显示面板及显示装置
CN112710942B (zh) * 2021-03-24 2021-06-08 上海伟测半导体科技股份有限公司 晶圆区域性问题的分析系统及方法

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US5126657A (en) * 1990-11-02 1992-06-30 Sun Microsystems, Inc. Apparatus for testing computer chips in the chips normal operating environment
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19936321C2 (de) * 1999-08-02 2003-12-24 Infineon Technologies Ag Anordnung und Verfahren zum Testen einer Vielzahl von Halbleiterchips auf Waferebene

Also Published As

Publication number Publication date
FR2700063A1 (fr) 1994-07-01
EP0606805A1 (de) 1994-07-20
FR2700063B1 (fr) 1995-02-10
DE69308804D1 (de) 1997-04-17
JPH0737947A (ja) 1995-02-07
US5608335A (en) 1997-03-04
EP0606805B1 (de) 1997-03-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee