DE69026809D1 - Verfahren zur Treibersteuerung integrierter Schaltungen während der Prüfung - Google Patents

Verfahren zur Treibersteuerung integrierter Schaltungen während der Prüfung

Info

Publication number
DE69026809D1
DE69026809D1 DE69026809T DE69026809T DE69026809D1 DE 69026809 D1 DE69026809 D1 DE 69026809D1 DE 69026809 T DE69026809 T DE 69026809T DE 69026809 T DE69026809 T DE 69026809T DE 69026809 D1 DE69026809 D1 DE 69026809D1
Authority
DE
Germany
Prior art keywords
procedure
integrated circuits
during testing
driver control
circuits during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69026809T
Other languages
English (en)
Other versions
DE69026809T2 (de
Inventor
Robert Walter Bassett
Pamela Sue Gillis
Panner Jeannie Theres Harrigan
Douglas Willard Stout
Mark Elliot Turner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69026809D1 publication Critical patent/DE69026809D1/de
Publication of DE69026809T2 publication Critical patent/DE69026809T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318513—Test of Multi-Chip-Moduls
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318577—AC testing, e.g. current testing, burn-in
    • G01R31/31858—Delay testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
DE69026809T 1990-01-25 1990-12-13 Verfahren zur Treibersteuerung integrierter Schaltungen während der Prüfung Expired - Fee Related DE69026809T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/471,249 US5127008A (en) 1990-01-25 1990-01-25 Integrated circuit driver inhibit control test method

Publications (2)

Publication Number Publication Date
DE69026809D1 true DE69026809D1 (de) 1996-06-05
DE69026809T2 DE69026809T2 (de) 1996-11-07

Family

ID=23870864

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69026809T Expired - Fee Related DE69026809T2 (de) 1990-01-25 1990-12-13 Verfahren zur Treibersteuerung integrierter Schaltungen während der Prüfung

Country Status (4)

Country Link
US (1) US5127008A (de)
EP (1) EP0438705B1 (de)
JP (1) JPH0777230B2 (de)
DE (1) DE69026809T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2551187B2 (ja) * 1990-02-08 1996-11-06 日本電気株式会社 スキャン動作実行方式
JPH06249919A (ja) * 1993-03-01 1994-09-09 Fujitsu Ltd 半導体集積回路装置の端子間接続試験方法
JP3319541B2 (ja) * 1994-03-29 2002-09-03 株式会社東芝 半導体集積回路装置
US5488319A (en) * 1994-08-18 1996-01-30 International Business Machines Corporation Latch interface for self-reset logic
SE9702176L (sv) * 1997-06-06 1998-12-07 Ericsson Telefon Ab L M En maskinvarukonstruktion för majoritetsval, samt test och underhåll av majoritetsval
US6260164B1 (en) 1998-07-31 2001-07-10 International Business Machines Corporation SRAM that can be clocked on either clock phase
DE19939595C1 (de) * 1999-08-20 2001-02-08 Siemens Ag Anordnung zum Testen einer Vielzahl von Halbleiterschaltungen
US7032146B2 (en) * 2002-10-29 2006-04-18 International Business Machines Corporation Boundary scan apparatus and interconnect test method
US7475320B2 (en) * 2003-08-19 2009-01-06 International Business Machines Corporation Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components
TW201439801A (zh) * 2013-04-08 2014-10-16 Hon Hai Prec Ind Co Ltd 電源電路容差設計最佳化系統及方法
CN111552599B (zh) * 2020-04-26 2024-04-09 武汉精测电子集团股份有限公司 一种分布式进程处理系统、半导体老化测试方法及系统、分布式系统
US11494540B1 (en) * 2021-03-26 2022-11-08 Cadence Design Systems, Inc. Method, system, and computer program product for implementing electronic design closure with reduction techniques

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4931723A (en) * 1985-12-18 1990-06-05 Schlumberger Technologies, Inc. Automatic test system having a "true tester-per-pin" architecture
JPS6329276A (ja) * 1986-07-23 1988-02-06 Hitachi Ltd 論理ｌｓｉ
US4782283A (en) * 1986-08-22 1988-11-01 Aida Corporation Apparatus for scan testing CMOS integrated systems
US4879718A (en) * 1987-11-30 1989-11-07 Tandem Computers Incorporated Scan data path coupling

Also Published As

Publication number Publication date
DE69026809T2 (de) 1996-11-07
EP0438705B1 (de) 1996-05-01
EP0438705A3 (en) 1992-07-15
US5127008A (en) 1992-06-30
JPH04125943A (ja) 1992-04-27
EP0438705A2 (de) 1991-07-31
JPH0777230B2 (ja) 1995-08-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee