DE3881964D1 - Verfahren fuer die pruefung der zuverlaessigkeit eines integrierten schaltungschips und eine schaltung zur durchfuehrung dieser pruefung. - Google Patents

Verfahren fuer die pruefung der zuverlaessigkeit eines integrierten schaltungschips und eine schaltung zur durchfuehrung dieser pruefung.

Info

Publication number
DE3881964D1
DE3881964D1 DE8888303946T DE3881964T DE3881964D1 DE 3881964 D1 DE3881964 D1 DE 3881964D1 DE 8888303946 T DE8888303946 T DE 8888303946T DE 3881964 T DE3881964 T DE 3881964T DE 3881964 D1 DE3881964 D1 DE 3881964D1
Authority
DE
Germany
Prior art keywords
test
circuit
chip
testing
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888303946T
Other languages
English (en)
Other versions
DE3881964T2 (de
Inventor
Robert W Shreeve
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE3881964D1 publication Critical patent/DE3881964D1/de
Application granted granted Critical
Publication of DE3881964T2 publication Critical patent/DE3881964T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2868—Complete testing stations; systems; procedures; software aspects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
DE88303946T 1987-05-18 1988-04-29 Verfahren für die Prüfung der Zuverlässigkeit eines integrierten Schaltungschips und eine Schaltung zur Durchführung dieser Prüfung. Expired - Fee Related DE3881964T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/051,888 US4855672A (en) 1987-05-18 1987-05-18 Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same

Publications (2)

Publication Number Publication Date
DE3881964D1 true DE3881964D1 (de) 1993-07-29
DE3881964T2 DE3881964T2 (de) 1993-10-28

Family

ID=21973977

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88303946T Expired - Fee Related DE3881964T2 (de) 1987-05-18 1988-04-29 Verfahren für die Prüfung der Zuverlässigkeit eines integrierten Schaltungschips und eine Schaltung zur Durchführung dieser Prüfung.

Country Status (6)

Country Link
US (1) US4855672A (de)
EP (1) EP0292136B1 (de)
JP (1) JP2871692B2 (de)
CA (1) CA1283489C (de)
DE (1) DE3881964T2 (de)
FI (1) FI881338A (de)

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US6137305A (en) * 1998-10-26 2000-10-24 Lucent Technologies Inc. Method and apparatus for testing laser bars
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US7248988B2 (en) 2004-03-01 2007-07-24 Transmeta Corporation System and method for reducing temperature variation during burn in
US6900650B1 (en) 2004-03-01 2005-05-31 Transmeta Corporation System and method for controlling temperature during burn-in
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US7371459B2 (en) 2004-09-03 2008-05-13 Tyco Electronics Corporation Electrical devices having an oxygen barrier coating
US7656173B1 (en) * 2006-04-27 2010-02-02 Utac Thai Limited Strip socket having a recessed portions in the base to accept bottom surface of packaged semiconductor devices mounted on a leadframe for testing and burn-in
US8487451B2 (en) * 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8492906B2 (en) * 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8125077B2 (en) * 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
US8063470B1 (en) 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
FR2933201B1 (fr) * 2008-06-30 2010-11-19 Airbus France Systeme et procede de deverminage d'equipements
US9947605B2 (en) * 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
US8334764B1 (en) 2008-12-17 2012-12-18 Utac Thai Limited Method and apparatus to prevent double semiconductor units in test socket
US8569877B2 (en) * 2009-03-12 2013-10-29 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US9449900B2 (en) * 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) * 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
RU2492494C2 (ru) * 2010-07-20 2013-09-10 Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Способ сравнительной оценки надежности партий интегральных схем
RU2538032C2 (ru) * 2010-07-20 2015-01-10 Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Способ сравнительной оценки надежности партий полупроводниковых изделий
RU2515372C2 (ru) * 2010-07-20 2014-05-10 Государственное образовательное учреждение высшего профессионального образования "Воронежский государственный технический университет" Способ разделения полупроводниковых изделий по надежности
CN102141597A (zh) * 2010-12-28 2011-08-03 天津电气传动设计研究所 Igct三电平中压变频器用功率单元试验电路
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9397031B2 (en) 2012-06-11 2016-07-19 Utac Thai Limited Post-mold for semiconductor package having exposed traces
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
FR3035750B1 (fr) * 2015-04-30 2018-06-15 Schneider Electric Industries Sas Dispositif de protection d'un reseau electrique
US10269686B1 (en) 2015-05-27 2019-04-23 UTAC Headquarters PTE, LTD. Method of improving adhesion between molding compounds and an apparatus thereof
US9805955B1 (en) 2015-11-10 2017-10-31 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple molding routing layers and a method of manufacturing the same
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
WO2022101870A1 (en) * 2020-11-13 2022-05-19 Eda Industries S.P.A Manufacturing method of semiconductor electronic devices based on operations on a lead-frame
CN114034945A (zh) * 2021-09-13 2022-02-11 中国航空无线电电子研究所 片上系统器件性能测试单元

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US3755888A (en) * 1972-07-17 1973-09-04 Westinghouse Electric Corp Method of testing modular electronic circuits
SU583413A1 (ru) * 1975-12-02 1977-12-05 Предприятие П/Я А-1298 Климатическа камера
US4145620A (en) * 1977-10-05 1979-03-20 Serel Corporation Modular dynamic burn-in apparatus
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SU972677A1 (ru) * 1980-08-12 1982-11-07 Предприятие П/Я Х-5618 Устройство дл контрол электропараметров радиодеталей
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
US4390598A (en) * 1982-04-05 1983-06-28 Fairchild Camera & Instrument Corp. Lead format for tape automated bonding
US4509008A (en) * 1982-04-20 1985-04-02 International Business Machines Corporation Method of concurrently testing each of a plurality of interconnected integrated circuit chips
US4573011A (en) * 1983-05-20 1986-02-25 Nouvas Manufacturing Technology Company Method and apparatus for testing electro-mechanical devices
US4612499A (en) * 1983-11-07 1986-09-16 Texas Instruments Incorporated Test input demultiplexing circuit
JPS6090684U (ja) * 1983-11-28 1985-06-21 株式会社椿本チエイン 通電負荷試験装置の給電装置
JPS60170946A (ja) * 1984-02-16 1985-09-04 Nec Corp 半導体集積回路
JPS6165445A (ja) * 1984-09-07 1986-04-04 Nec Corp 半導体装置
JPS61185949A (ja) * 1985-02-13 1986-08-19 Sharp Corp フイルムキヤリアにアツセンブリされた半導体集積回路のエ−ジング方法
JPH034032Y2 (de) * 1985-09-19 1991-02-01
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JP3760194B2 (ja) * 1996-06-13 2006-03-29 ヤンマー建機株式会社 走行車輌の操向操作機構

Also Published As

Publication number Publication date
US4855672A (en) 1989-08-08
FI881338A (fi) 1988-11-19
JPS63301540A (ja) 1988-12-08
CA1283489C (en) 1991-04-23
DE3881964T2 (de) 1993-10-28
FI881338A0 (fi) 1988-03-21
EP0292136A1 (de) 1988-11-23
JP2871692B2 (ja) 1999-03-17
EP0292136B1 (de) 1993-06-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8339 Ceased/non-payment of the annual fee